LAr Pix ASIC Testing at Caltech Leon Mualem

LAr. Pix ASIC Testing at Caltech Leon Mualem Caltech

LAr. Pix. V 2 Testing needs • ASICs on hand - 2500 parts - Serial numbered and barcode engraved • Socket board - tests one ASIC at a time. - Penn socket boards arrived yesterday. - Hope to assemble and ship to Peter next week. - Socket board has same interface/connector as tile test boards • • • Cables from socket board to Pac. Man-v 1 Controller (Pac. Man-v 1) - command/control readout ASIC to computer Computer for interface Power supply for custom electronics Testing software Aug 27 2020 LAr. Pix Mtg

LAr. Pix. V 2 Testing needs Met Aug 27 2020 LAr. Pix Mtg

LAr. Pix. V 2 Testing status • After some iteration on setup with Peter (THANKS!) the system and chip in socket board are working • • - Can configure hydra communication - Can program ASIC registers and verify configuration - Can read out data packets Working on conversion of LAr. Pix. V 1 test programs to V 2. Small changes to register names, global_threshold->threshold_global Adjust code to 64 channels/ASIC, up from 32 New packets (Sync Packet) crashed some analysis routines, better filtering (in software) now allows them to run smoothly • Working through all tests to get them to run reliably - Channel rate vs. threshold is working well - Baseline measurement almost finished • Previously used external trig Aug 27 2020 LAr. Pix Mtg

LAr. Pix. V 2 Testing Status • Complete testing code conversion • Finalize test output data • Determine test time for each test - ~1 min pedestal - ~8 min Rate. Vs. Thresh • Run a sample batch through pedestal mean/RMS (28) • Run a smaller sample batch through above+Rate. Vs. Thresh (10) • Begin production run testing - Target rate depending on needs, aiming for ~200/week average Aug 27 2020 LAr. Pix Mtg

LAr. Pix. V 2 Testing Summary • 0 DOA on first 38 • 2 with one bad channel each (saturated) • Noise on channels appears consistent - Need to look more closely at details Aug 27 2020 LAr. Pix Mtg

LAr. Pix. V 2 Testing Summary • 0 DOA on first 38 • 2 with one bad channel each (saturated) • Noise on channels appears consistent - Need to look more closely at details Aug 27 2020 LAr. Pix Mtg

Aug 27 2020 LAr. Pix Mtg

Aug 27 2020 LAr. Pix Mtg

Aug 27 2020 LAr. Pix Mtg

Aug 27 2020 LAr. Pix Mtg

Aug 27 2020 LAr. Pix Mtg

Aug 27 2020 LAr. Pix Mtg

Aug 27 2020 LAr. Pix Mtg

Aug 27 2020 LAr. Pix Mtg

Aug 27 2020 LAr. Pix Mtg

Aug 27 2020 LAr. Pix Mtg

LAr. Pix. V 2 Testing Summary • 0 chips DOA on first 38 • 2 with one bad channel each (saturated at 255) • Noise on channels appears to be consistent chip to chip - Certainly correlated - Need to look more closely at details Aug 27 2020 LAr. Pix Mtg

LAr. Pix. V 2 Testing Plans/Questions • Additional tests? - Test All communications channels (4 hydra channels)? • Probably would not increase time to test significantly if valuable - Repeat pedestal and/or threshold testing on additional channels? • Would increase testing time / reduce throughput • What to ship? - Testing/shipment batches in groups of 90, based on carriers - 180 -270 with functional test/noise msmt could ship on Monday Aug 27 2020 LAr. Pix Mtg