Laboratoire de Physique Corpusculaire Caen Journes VLSIPCBFPGAIAOCAO IN

Laboratoire de Physique Corpusculaire - Caen Journées VLSI–PCB–FPGA–IAOCAO IN 2 P 3 FEAST Front-End Asic for Snemo Tracker Sébastien Drouet, Laurent Leterrier LPC Caen, ENSICAEN, Université de Caen, CNRS/IN 2 P 3, Caen, France June, 7 th 2011 SNEMO Collaboration Meeting, 10/27/2011 S. Drouet – sdrouet@lpccaen. in 2 p 3. fr

FEAST OUTLINE 1. Overview 2. Main specifications 3. ASIC Diagrams 4. ASIC Layout 5. Status 6. Conclusion 2 S. Drouet – sdrouet@lpccaen. in 2 p 3. fr

1. Overview FEAST A Super. NEMO module (x 20) § 5 kg of source (82 Se) § Tracker: Drift chamber of 2000 Geiger cells § Calorimeter: 550 PVT scintillators + 8" PMTs Installation of a module for 2014 in LSM. 3 S. Drouet – sdrouet@lpccaen. in 2 p 3. fr

2. Main specifications FEAST • Technology: 0. 35µm CMOS Austriamicrosystem • 54 channels corresponding to 18 or 27 geiger cells depending of the configuration • 3 types of channel: Anodic, Cathodic or Generic Channel • Configurable gain (20/40/60 or 80) for all amplifiers • Common configurable thresholds for all discriminators • Registers: Ø Depth of 5 for anodic and 1 for cathodic Ø Length of 64 bits • Time resolution: 12. 5 ns (48 -bit Gray counter @ 80 MHz) • Output Bus: 16 bits @ 10 MHz (token ring system) • Trigger information: 27 bits @ 40 MHz = 675 ns (shift registers) 3 • Slow-Control: 2 shift registers, one with 255 bits and the other with 193 bits, running @ 10 MHz S. Drouet – sdrouet@lpccaen. in 2 p 3. fr

FEAST 3. ASIC Diagram 10 -bit DACs Anodic Input CH 0 AC Cathodic Input CH 1 CC Anodic or Cathodic Input CH 2 48 -bit Timestamp Counter Slow-Control Register (more than 430 bits) 80 MHz Not_Empty_Anode_Memory GC Readout Cathodic Input CH 3 Not_Empty_Cathode_Memory Token_Go Data_Reg_Ready Data_Read Data_Out CC Anodic Input CH 4 AC Cathodic Input CH 5 CC Upto CH 53 with the same struture of 6 channels AC = Anodic Channel CC = Cathodic Channel 4 GC = Generic Channel, can be configurated in Anodic or Cathodic mode 16 bits Token_Back Common. Test. Input 54 inputs (6 x 9) ‘VLNT’ & ‘VHPT’ 10 -bit DAC ‘VCPT’ SC_En. Debug SC_Chip. Select SC_CLK SC_Data. IN SC_Load SC_Data. Out SC_Read. Mem Trigger System (27 or 18 bits) Authorized Channels in anodic mode Lock_Trig_Register Trig_Clock Trig_Shift_Out Trig_Channels for building Trigger information S. Drouet – sdrouet@lpccaen. in 2 p 3. fr

3. ASIC Diagram Common to 54 channels Anodic Channel Diagram Digital_Probe_4 Select_Offset_Ch. X<1: 0> Analog_Probe_3 n. En_Ch. X VLNT Analog_Probe_4 Voltage adder Comparator Negatif Pulse Detector Anodic<X> Low-pass Amplifier G=20 BW = 2 MHz VOffset_AC_1 48 -bit Counter 80 MHz Band-pass Amplifier G=1/2/3/4 BW = 1. 5 MHz VOffset_AC_2 Select_Gain_Ch. X<1: 0> VHNT Comparator Negatif Pulse Detector VHPT Comparator Positif Pulse Detector OR OR OR I n h i b i t i o n Digital_Probe_3 Register(4 x 16 bits): 48 bits: Time. Stamp 2 bits: Chip_ID 6 bits: Channel_ID 3 bits: Register_ID 1 bit: Mode (A or C) 4 bits: unused TS Register (Depth 1) Token_Go TS Register (Depth 2) Data_Reg_Ready Readout Data_Read Data_Out<15: 0> Token_Back TS Register (Depth 2) Delay 115µs Digital_Probe_2 FEAST Not_Empty_Anode_Memory Common. Test. Input n. Valid_Trig_Ch. X Trig sequencer Trig Shift Register (27 or 18 bits) Lock_Trig_Register Trig_Clock Trig_Shift_Out Trig_Channels VHPT VLNT VHNT 5 S. Drouet – sdrouet@lpccaen. in 2 p 3. fr

FEAST 3. ASIC Diagram Cathodic Channel Diagram Common to 54 channels The channel is only dedicated to cathodic signals. The selection of the gain is common to all the cathodic channels Analog_Probe_1 or Analog_Probe_2 VOffset_CC_1 VOffset_CC_2 Register (4 x 16 bits): 48 bits: Time_Stamp 2 bits: Chip_ID 6 bits: Channel_ID 3 bits: Register_ID 1 bit: Mode (A or C) 4 bits: unused 48 -bit Counter 80 MHz VCPT Token_Go Cathodic<X> Low-pass amplifier G=20 BW = 2 MHz Band-pass amplifier G=1/2/3/4 BW = 1. 5 MHz Sel_CC_Gain<1: 0> Comparator Positive pulse Detector OR Inhibition Data_Reg_Ready TS Register (Depth 1) n. En_Ch. X Readout Data_Read Data_Out<15: 0> Token_Back Digital_Probe_1 or Digital_Probe_5 Common. Test. Input Not_Empty_Cathode_Memory 6 S. Drouet – sdrouet@lpccaen. in 2 p 3. fr

FEAST 3. ASIC Diagram Common to 54 channels Generic Channel Diagram 48 -bit Counter 80 MHz Digital_Probe_4 Not_Empty_Cathode_Memory Select_Offset_Vlnt_Ch. X<1: 0> Analog_Probe_2 n. En_Ch. X VLNT Analog_Probe_4 Voltage adder Comparator Negatif Pulse Detector Generic<X> VOffset_AC_1 VOffset_CC_1 VOffset_AC_2 VOffset_CC_2 Low-pass Amplifier G=20 BW = 2 MHz Register (4 x 16 bits): 48 bits: Time. Stamp 2 bits: Chip_ID 6 bits: Channel_ID 3 bits: Register_ID 1 bit: Mode (A or C) 4 bits: unused VHNT Band-pass Amplifier G=1/2/3/4 BW = 1. 5 MHz Select_Gain_Ch. X<1: 0> Comparator Negatif Pulse Detector VHPT VCPT Comparator Positif Pulse Detector OR OR OR I n h i b i t i o n TS Register (Depth 1) Token_Go TS Register (Depth 2) Data_Reg_Ready Readout Data_Read Data_Out<15: 0> Token_Back TS Register (Depth 2) Delay 115µs Not_Empty_Anode_Memory Digital_Probe_5 Digital_Probe_2 External Trigger Trig sequencer Common. Test. Input Select_Type_Ch. X 7 Trig Shift Register (27 or 18 bits) Lock_Trig_Register Trig_Clock Trig_Shift_Out Trig_Channels n. Valid_Trig_Ch. X S. Drouet – sdrouet@lpccaen. in 2 p 3. fr

FEAST 4. ASIC Layout • Layout of Cathodic Channel (2170 µm x 230 µm) Low-pass Amplifier Comparator Slow Control Band-pass Amplifier 1 Register + Readout • Layout of Anodic Channel (2170 µm x 401 µm) Voltage Adder 8 Low-pass Amplifier 3 Comparators Band-pass Amplifier Slow Control 5 TS Registers + Readout + Trigger System S. Drouet – sdrouet@lpccaen. in 2 p 3. fr

4. ASIC Layout 10 -bit DACs Counter@80 MHz 10 -bit DACs FEAST Buffers for analogue probes Global Layout • Dimension: 5000 µm x 7700 µm (38. 5 mm²) Amplifiers • 160 pins • Layout simulation with ULTRASIM • Submission: December 2011 9 Discriminators Registers & Logic for all channels Slow-control registers S. Drouet – sdrouet@lpccaen. in 2 p 3. fr

FEAST 5. ASIC Status • Tests already done • Consumption: 3. 3 V / 270 m. A. • Slow-control working at 10 MHz. • Reading the trigger word at 40 MHz. • 16 -bit Output Bus working at 10 MHz. • Common Test Input. Digital part OK • Tests in progress • Characterization of the analog stages • To be done: 10 • Measuring the time resolution. S. Drouet – sdrouet@lpccaen. in 2 p 3. fr

FEAST 6. Conclusion • Tests réalisés satisfaisants, caractérisation à finir. • Intégration de 2 ASICs sur la carte front-end du tracker de SNEMO par nos collègues de l’Université de Manchester. (fin juin 2012). • Production et test d’une série de 150 puces pour le prototype de SNEMO (équivalent à environ 8000 voies) pour 2013. 11 S. Drouet – sdrouet@lpccaen. in 2 p 3. fr