Laboratoire de lAcclrateur Linaire IN 2 P 3
Laboratoire de l’Accélérateur Linéaire (IN 2 P 3 -CNRS) Orsay, France October 5 th 2010 Olivier Duarte Tests Front-end card Status u Test Front-end board n n Test board architecture. Test bench. u Firmware architecture u DAQ Idea u Status of the firmware Block n n Test Firmware blocks LHCb upgrade meeting
Tests board architecture Testsfor board architecture Schedule SPECS development Board size : 305 mm x 155 mm 10 layers IN / OUT (NIM) USB Delay Chip SPEC Mezzanine A 3 PE 1500 REGULATORS AX 500 Analog Mezzanine 120 mm x 120 mm "LAL Support" for AX 500 Olivier Duarte LHCb upgrade meeting
Test bench Olivier Duarte LHCb upgrade meeting
Firmware architecture (indevelopment prototype tests : A 3 PE 1500) schedule SCROC chedule for SPECS All Blocks inside A 3 PE 1500 in Verilog language I 2 C 1 I 2 C 2 I 2 C 3 I 2 C 4 USB / I 2 C module USB Interface Tests register 16/32 bits Rd/Wr Delay chip LAL (x 3) Delay chip CERN (x 3) AX 500 FPGA Analog mezzanine Step 1 : used the board with power supply Status Register and clock Ctrl Reset Register Step 2 : Add trigger and Delay Chip Ctrl Register In Ext Clk Q : 40 Mhz Clock Ctrl Step 3 : Add data processing and DAQ Global Clk (Diff 40 Mhz) USB Clk (10 Mhz) SPECS Clk Out Ext Clk Trigger System Data FIFO/RAM Clock Divider ADC Data processing - ADC Data - Test value injection -Re-synchronize ADC Input -Dynamique pedestral subtraction Version : 07/10/2020 19: 26 Olivier Duarte LHCb upgrade meeting October 5 th 2010
DAQ Idea … u Inside A 3 PE 1500 Ctrl_Register (16 b) n 1 0 u 60 blocks of 4608 Bit For DAQ 12 x 3 Blocks RAM to ADC data FIFO n 2 Blocks RAM to enable ADC data n Start acquisition (ADC running) USB Interface FIFO 12 ADC Data input 8 O_Enable ADC Channels or NIM connector (18 x 768) To One ADC Channel 3 x RAMBlock of 18 x 256 Enable ADC RAM / FIFO Block for all channels FIFO Full 1 Status_Register (16 b) A 3 PE Firmware LHCb upgrade meeting DAQ sequence Load RAM sequence n USB Interface write the start_acquisition bit in the Ctrl_Register n ADC running n ADC data are writing in FIFO n When the FIFO is full we write FIFO_full bit in the Status_register n The PC scrutinize the status register and when the FIFO_full bit is high the USB read the FIFO n When the FIFO is empty we can start new acquisition n FIFO Empty (8 x 768) Olivier Duarte u PC October 5 th 2010
Tests Status u Download A 3 PE 1500 with Flash. Pro 4 ok (Problem solved) u Rd / Wr register by USB inside A 3 P ok Used “test_245” by Chafik n Tests with 16 and 32 bits Rd/Wr register inside A 3 PE 1500 n Rd / Wr Status, Ctrl, Reset register and clock ctrl implementation u u Two board available (one tested) ok (One for Carlos Test. Bench) Olivier Duarte to do October 5 th 2010
Status of the firmware blocks All Blocks inside A 3 PE 1500 in Verilog language u Clock divider and trigger generator module for Lemo outputs Step 2 (to adapt from the CROC by Olivier) u I 2 C Module u Processing ADC data (in progress by Christophe) u Data storage (to do by Jimmy) Step 3 u Test value injection RAM (to do by Jimmy) Step 3 Olivier Duarte (to adapt from Jihane’s code by Olivier) LHCb upgrade meeting October 5 th 2010 Step 2 Step 3
SPARE Olivier Duarte LHCb upgrade meeting
SPARE Olivier Duarte LHCb upgrade meeting
SPARE Olivier Duarte LHCb upgrade meeting
SPARE Olivier Duarte LHCb upgrade meeting
Tests board powerdevelopment prototype tests : supply schedule SCROC chedule for SPECS P 7 V Regulator - 4913 AVCC_1 for Analog Mezza (+3 to +5 V) Regulator - 4913 AVCC_2 for Analog Mezza (+3 to +5 V) DVDD for Analog Mezza (+2 V 5 to +3 V 3) Regulator - 4913 VCC for board (+5 V) Regulator - 4913 P 3 V 3 for board (+3, 3 v) (Vcc. IO bank fixe) Regulator - 4913 M 7 V P 1 V 5 for FPGA core Regulator - 4913 1, 5 v < Vcc. IOB_Var < +2, 5 v) Regulator - 4913 P 2 V 5 for bank (+2, 5 v) (Vcc. IO bank variable) (Vcc. IO bank LVDS) Regulator - 7913 AVEE for Analog Mezza (-3 to -5 V) Regulator - 7913 VEE for board (-5 V) {NIM translators} Ø Lab. Power Supply input (+/- 7 V) Ø 10 Radiation tolerance regulators ! ! Olivier Duarte LHCb upgrade meeting
Tests board Clockdevelopment prototype tests : Tree schedule SCROC chedule for SPECS • Each FPGA receive 2 adjustable Clock (LVDS) • Analog mezzanine receive also 2 adjustable Clock (LVDS) • Each ADC_Channel receive 1 Clock (LVDS) Olivier Duarte LHCb upgrade meeting
A 3 PE firmware blocks : USB interface module u USB interface module USB Interface standard module n I 2 C modules (x 4) n FT 245 side USB_Data[7. . 0] RXF User side USB Interface Standard module Sub. Add[6. . 0] User. Data[7. . 0] TXE N_Write N_Read N_Sync WR Interrupt RD Clk N_Reset Olivier Duarte LHCb upgrade meeting USB / I 2 C module Sda Scl Delay chip LAL (x 3) USB / I 2 C module Sda Scl Delay chip CERN (x 3) USB / I 2 C module Sda Scl AX 500 USB / I 2 C module Sda Scl Analog mezzanine
A 3 PE firmware blocks : Clock divider and trigger generator u Clock divider n u 50 ns to 0. 4 s (24 bits counter) Internal Trigger With this module we can produce trigger (external trigger or software command) Registers loaded by USB or SPECS : Olivier Duarte Tdelay (8 bits) TL 0 (16 bits) LHCb upgrade meeting Registers loaded by USB or SPECS : Ndump (8 bits) Nspy (8 bits)
A 3 PE firmware blocks : data processing u Processing ADC data Re-synchronize ADC input n Dynamique pedestal subtraction n Ø u Suppression of low frequency noise Trigger processing Convert ADC data to 8 bit n Sent towards the TRIG-PGA n AX 500? RAM block 8 x 16 x 256 Olivier Duarte LHCb upgrade meeting
A 3 PE firmware blocks : RAM u Data storage (output buffer) before readout 8 x 16 (12 used) x 256 n Read only by USB (first !) n u Test value injection RAM 8 x 16 (12 used) x 256 n Use of the RAM test describ in LHCb ECAL/ HCAL Front-End card n There exist different ways to use the RAM test: - The standard one: the RAM address is increased every 25 ns by the clock and the sequence of 256 addresses is initiated by the test-sequence signal, originating in the calibration command of the channel B and enabled by the corresponding status of an I 2 C register. The sequence ends up after 256 clock cycles. - A variant with an enable loop bit loaded by I 2 C. In this case after the sequence initialisation the RAM address counter continues advancing and jumps automatically from address 255 to address 0. - The L 0 mode where the RAM address is incremented upon reception of each L 0. The sequence can be terminated at 255 or looped as in case 2. - Calibration mode where the RAM address is incremented upon reception of test sequence command. In this case by definition the system will loop after address 255. Olivier Duarte LHCb upgrade meeting
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