Lab 5 JK Flip Flop and Counter Fundamentals

Lab 5 : JK Flip Flop and Counter Fundamentals: Slide 2 JK Flip-Flop. Slide 3 Three stage ripple counter. Slide 4 Down Counters. Slide 5 Up/Down Counters. Slide 6 Altera 4 count Symbol. Slide 7 Cascading 4 count Symbols. Slide 8 BCD Numbers. Slide 9 Frequency Division Slide 10 Frequency Division and the UP-1 board.

Lab 5: The JK Flip Flop : The JK flip flop is an improved SR flip flop. The improvement is the replacement of the Ambiguous mode with the Toggle mode. The Set, Reset and No Change modes are still used. The JK flip flop in the example has a negative edge triggered clock. J Q >Clk K Q J K 0 0 No Change 0 1 Reset or Kill To help remember the RESET mode you can think of “K=1” means KILL the output. Set or Jump To help remember the SET mode you can think of “J=1” means the output will JUMP high. 1 0 1 1 Q Toggle J=1 and K=1 is called the TOGGLE mode. The AMBIGUOUS mode has been removed. TOGGLE = Change the output logic level. -If Q starts at 0 then Q will toggle high. -If Q starts at 1 then Q toggle low. If you study the construction diagram of the JK flip flop you can see how the TOGGLE mode works. Begin by connecting J=K=1. TOGGLE Mode. Assume Q =0 is the initial condition 1 1 0 S Q Trace the logic levels back through the AND gates. 1 J Write the logic levels at the output of the AND gates. >Clk 1 0 0 1 1 R Q Inside the JK flip flop there is an SR flip flop ready to K 0 set the output to logic 1 when the clock is asserted. Proceed and you will see the output Q toggle and you Slide #2 will also see how the internal SR is setup to toggle again if a second clock pulse was asserted.

Lab 5 : Three Stage Ripple counter : JK flip flops connected in the toggle mode can be connected together to create a binary counter system. Start with one JK flip flop, apply a clock waveform and sketch the Q output response. Assume PRE and Clr has been disabled (=1) on all flip flops. Input 1 1 0 J Qa >Clk K Qa 1 1 1 2 J Qb >Clk K Qb 3 1 1 4 J Qc >Clk K Qc 5 Qa Qa will toggle on each negative edge of the input clock. Connect Qb will toggle a second on each stagenegative to output edge Qa. of Qa. Qb Connect Qc will toggle a thirdonstage eachto negative output edge Qb. of Qb. Qc 6 7 In Qc Qb Qa 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 Label the input clock pulses from 0 to 7 and place the counter response in a table. The table is called a COUNT state table. The counter is called a MOD 8 counter because it has 8 different count states. The counter restarts at 0, 0, 0 after clock input 7. MOD is short for the word MODULUS. Connect the flip flop outputs to 3 LED’s and you will see a binary count sequence from 0 … to … 7. The speed at which the counter counts is controlled by the input clock. 1 PPS input clock will display the 0 to 7 count sequence on the LED’s in 8 seconds. Each count state would last 1 sec. If the clock input was 1000 PPS then all 3 LED’s would appear to be constantly on at the same time. A count cycle would take Slide #3 8 milli. Sec. Too fast to be visible on the 3 LED’s.

Lab 5: Down Counters : To make a counter count backwards all you need to do is to connect the Q to the Clk of the next flip flop. Input 1 1 J Qa >Clk K Qa 1 1 J Qb >Clk K Qb 1 1 J Qc >Clk K Qc In Qc Qb Qa Qa toggles 0 on 0 every 0 0 negative edge of the input clock. 1 1 Qa Qa Qb Qc If you place the count states in a table you can see the down count sequence. Slide #4 2 on 1 every 1 0 Qb toggles negative 3 edge 1 of Qa. 0 1 A negative 4 edge 1 on 0 Qa 0 is the same as the positive edge 0 1 1 Qa. 5 Qc toggles 6 on 0 every 1 0 negative edge of Qb. Which is the same as 0 the 0 positive 7 1 edge of Qb.

Lab 5: Up/Down Counter : This system combines the features of both an up and a down counter. The system has a count direction control input to select up counting or down counting. 1 0 1 1 J Qa >Clk K Qa Qa • 1 0 1 0 0 1 Qa • 1 1 J Qb >Clk K Qb Qb • 1 0 0 1 1 J Qc >Clk K Qc Qb • 1 0 1 Up/Down When the control input is low, the top AND gates will pass the logic levels from the Q outputs. The bottom AND gates output 0. The OR gate outputs a Q • 1+0 = Q. This connects Q to clock and the counter counts up or forward. When the control input is high, the bottom AND gates pass the logic levels from the Q outputs. The top AND gates output 0. The OR gate outputs a Q • 1+0 = Q. This connects Q to clock and the counter counts down or backwards. Slide #5

Lab 5: Altera 4 Count Symbol: The Altera 4 count symbol can be found in the mf library. It is very similar to a VHDL binary counter. Apply a pulse waveform to the positive edge triggered clock input and it counts from 0 to 15. Step 15 Step 1: : 2 3 4 Place number Assert Disable Enable Apply 4 load up at inputs and place load counting down clock and number at 10 clear counting pulses 0 inputs 1 1 0 6 0 1 Step 2: Assert SETN CLRN 0 1 01 4 count LDN A B C D CIN DNUP SETN CLRN CLK QA QB QC QD COUT Synchronous Load: LDN and ABCD and Clock: LDN=0 loads a number into Qa, Qb, Qc, Qd from A, B, C, D on positive edge of clock. LDN=1 disables the load feature. Clock is used for counting. The animation will demonstrate how to load the number 6 into the counter. 1 1 0 0 0 1 1 0 Step 2: Assert Clock Asynchronous Load: SETN and ABCD: SETN=0 loads a number into Qa, Qb, Qc, Qd from A, B, C, D immediately. The clock is not required. SETN =1 disables the load feature. Clock is used for counting. The animation will demonstrate how to load the number 6 into the counter. Asynchronous Clear: CLRN=0 resets (clears) Qa=Qb=Qc=Qd =0. Clock not required CLRN =1 disables the clear feature. Clock is used for counting. Count Direction: DNUP=0 Counter counts forward or up (0, 1, 2…). DNUP=1 Counter counts backwards or down (15, 14, 13…). The animation will demonstrate an up count sequence to 4 and then a down count sequence back to 0. The count sequence can be reversed at any time. CIN and COUT: Carry in and Carry out are used to cascade counter symbols. Cascading will be explained in an upcoming lab. Altera Default Values: Slide #6 Altera connects LDN, SETN, CLRN, DNUP and CIN to 1 if they are left unconnected in a drawing. These are called default values. The default values will make the counter count down and disable the loading and clearing functions.

Lab 5: Cascading 4 count Symbols: Two 4 count symbols can be cascaded to create an 8 -bit counter system. CIN and COUT are carry input and carry output. They are used to cascade stages. One 4 count symbol is a Mod 16 counter. (0 … 15). Two 4 count symbols is Mod 256 (16 x 16). 4 count 0 LDN A B C D CIN DNUP SETN CLRN CLK QA QB QC QD COUT 4 count 10 1 0 1 0 LDN A B C D CIN DNUP SETN CLRN CLK QA QB QC QD COUT 0 0 0 1 0 Connect COUT to CIN. Connect the clocks together. COUT is the carry output. It is 0 when the count is 0 to 14. It is 1 when the count is 15. A carry out is generated at 15 because the counter is about to recycle back to 0. CIN is the carry input. The counter counts at every positive edge of the clock when CIN=1. The counter holds if CIN=0. CIN=1 is the default value if the input is not connected. It takes 14 clock pulses to cycle the first counter from 0 to 14. During this time COUT =0 and because the second counter has CIN =0 it does not count. On the next clock pulse, the first counter reaches 15 and then changes COUT to 1. On the next clock pulse, the first counter cycles back to 0 and the second counter counts to 1 because CIN was 1. COUT then changes back to 0. The 8 -bit counter system cycles the first 4 count symbol’s bits from 0 to 15 continuously. The second 4 count symbol only counts when there is a carry out signal from the first stage. It takes 256 clock pulses to completely Slide #7 cycle the counter from 0 to 255.

Lab 5: BCD Numbers : A BCD number is a Binary Coded Decimal number. It is a 4 bit code used to represent the decimal numerals 0, … 9. The 4 bit numbers above 9 are not used in this number system. Converting decimal to BCD: Example: convert 25 to BCD 8 4 2 1 0 0 0 0 1 0 =0 1 =1 0 =2 0 0 0 1 1 1 1 0 0 1 0 1 Slide #8 1 0 1 02151 1 1 0 0 1 0010 1 0 0101 1 Convert each decimal numeral to BCD. =3 =4 =5 =6 =7 =8 =9 4 bit numbers for 10, 11, … 15 are not used! 1 125 1 0 Thus = 00100101 BCD 1 1 : Converting to decimal Example: convert 0110010111 BCD to decimal. Start at the BCD point and group BCD bits into blocks of four. Convert each block into a BCD number. 0110010111 7 9 1 Thus 0110010111 BCD = 197

Lab 5 : Frequency Division: Frequency of a pulse waveform is its pulse rate. A counter halves the frequency of the input clock at each of its outputs. 8 PPS Input 1 1 0 J Qa >Clk K Qa 1 J Qb >Clk K Qb 2 3 J Qc >Clk K Qc 4 6 7 8 PPS Qa 4 PPS Qb 2 PPS Qc 1 PPS 1 Second Slide #9 5 1 PPS Mod 8 counter is also called a divide by 8 counter

Lab 5 : Frequency Division and the UP board: The UP-1 board has a 25, 1275, 000 PPS oscillator. Connecting a counter to a set of LED’s and clocking the counter at this fast rate would result in a count that would not be distinguishable on the LEDS. All LED’s would appear to be on at the same time. UP-1 Oscillator >CLK 25, 175, 000 PPS UP-1 Oscillator 25, 175, 000 PPS Slide #10 >CLK Q 0 Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 Q 8 Q 9 Q 10 Q 11 Q 12 Q 13 Q 14 Q 15 Q 16 Q 17 Q 18 Q 19 Q 20 Q 21 Q 22 Q 23 Q 24 QA QB QC QD Connecting the UP oscillator to a 24 stage counter will divide the Thedown counter 16 isclock pulses to count from Grouping frequency to arequires rate that distinguishable on LED’s. 0 to 15. Each second the oscillator generates any 4 adjacent outputs creates a MOD 16 counter. Each MOD 16 pulses. LED’sspeed. are changing so fast that counter 25, 175, 000 group counts a slower they all appear to be on at the same time. Mod Mod 16 counter with a 25, 175, 000 PPS clock rate. 16 counter with a 12, 587, 500 PPS clock rate. 16 counter with a 6, 293, 750 PPS clock rate. 16 counter with a 3, 146, 875 PPS clock rate. Pulse rates must be less than 30 PPS in order to be distinguishable on LED’s. 24 PPS 12 PPS 6 PPS 3 PPS 1. 5 PPS 0. 75 PPS Mod 16 counter with a 48 PPS clock rate. Mod 16 counter with a 24 PPS clock rate. Mod 16 counter with a 12 PPS clock rate. Visible on LED’s!