Lab 1 To generate layout for CMOS Inverter

Lab 1: To generate layout for CMOS Inverter circuit and simulate it for verification.

VLSI Lab VLSI LABORATORY FRONT END DESIGN (CAD) BACK END DESIGN (CAD) TECHNOLOGY (TCAD)

A complete VLSI lab set up should contain Proper hardware Proper software Foundry or link up with some fab lab Test facility Purpose

DESIGN STEPS • • • SCHEMATIC LAYOUT DESIGN DRC LAYOUT Vs SCHEMATIC PARASITIC EXTRACTION POST LAYOUT SIMULTION

List of Experiments 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. To generate layout for CMOS Inverter circuit and simulate it for verification. To prepare layout for given logic function and verify it with simulations. Introduction to programmable devices (FPGA, CPLD), Hardware Description Language (VHDL), and the use programming tool. Implementation of basic logic gates and its testing. Implementation of adder circuits and its testing. Implementation of J-K and D Flip Flops and its testing. Implementation 4 to 1 multiplexer and its testing. Implementation of 3 to 8 decoder and its testing. Implementation of sequential adder and its testing. Implementation of BCD counter and its testing. Simulation of CMOS Inverter using SPICE for transfer characteristic. Simulation and verification of two input CMOS NOR gate using SPICE. Introduction to Block Diagram Mathod Design of digital Logic using block diagram.

Project • Mini Project: VHDL/Verilog based mini project with emphasis on design and implementation into the group of maximum 3 students.

Design Abstraction Levels SYSTEM MODULE + GATE CIRCUIT DEVICE G S n+ D n+

Microwind • Microwind is a tool for designing and simulating circuits at layout level. The tool features full editing facilities (copy, cut, past, duplicate, move), various views (MOS characteristics, 2 D cross section, 3 D process viewer), and an analog simulator

Tools from Microwind • • Microwind DSCH Microwind 3 Editor Microwind 2 D viewer Microwind 3 D viewer Microwind analog simulator Microwind tutorial on MOS devices View of Silicon Atoms

Getting Microwind • Go to the website http: //www. microwind. net/document • Download the freeware version of the microwind • Unzip the files in a Folder

Microwind Downloads

INTRODUCTION THE TOOL User-friendly and intuitive design tool for educational use. The student draws the masks of the circuit layout and performs analog simulation The tool displays the layout in 2 D, static 3 D and animated 3 D

Our Approach MOS DEVICE Traditional teaching : in-depth explanation of the potentials, fields, threshold voltage, and eventually the expression of the current Ids Our approach : step-by-step illustration of the most important relationships between layout and 1. 2. 3. 4. 1. 2. performance. Design of the MOS I/V Simulation 2 D view Time domain analysis 3. 4.

Feature Size • Chips are specified with set of masks • Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) • Feature size f = distance between source and drain • Set by minimum width of polysilicon • Feature size improves 30% every 3 years or so • Normalize for feature size when describing design Rules • E. g. λ = 0. 090 μm in 0. 180 μm process

Layout design rules: For complex processes, it becomes difficult to understand the intricacies of the fabrication process and interpret different photo masks. They act as interface between the circuit designer and the process engineer.

Microwind Environment Menu Command One dot on the grid is 5 lambda or 0. 30 µm Editing Icons Access to Simulation Layout Library 2 D 3 D Views Simulation Properties Palette of Layers Work Area Active Layers Current Technology

Design Rules N- Well r 101 r 102 r 110 Minimum width Between wells Minimum well Area r 101 N - Well r 102 12λ 12 λ 144 λ 2

r 201 Minimum N+ and P+ diffusion width 4λ r 201 P+ Diff r 201 N+ Diff N - Well

r 202 Between two P+ and N+ diffusions r 202 P+ Diff N - Well r 202 N+ Diff 4λ

r 203 Extra N-well after P+ diffusion r 203 P+ Diff r 203 N - Well N+ Diff 6λ

r 204 Between N+ diffusion and n-well P+ Diff N - Well r 204 N+ Diff 6λ

r 210 Minimum diffusion area r 210 P+ Diff r 210 N+ Diff N - Well 16λ 2

r 301 Polysilicon Width 2λ Polysilicon r 301 P+ Diff N - Well Polysilicon r 301 N+ Diff

r 302 Polysilicon gate on Diffusion Polysilicon r 302 P+ Diff N - Well Polysilicon r 302 N+ Diff 2λ

r 307 Extra Polysilicon surrounding Diffusion 3λ Polysilicon r 307 P+ Diff r 307 N - Well Polysilicon r 307 N+ Diff r 307

r 304 Between two Polysilicon boxes Polysilicon r 304 P+ Diff N - Well Polysilicon r 304 N+ Diff 3λ

r 307 Diffusion after Polysilicon r 307 P+ Diff N - Well Polysilicon r 307 N+ Diff 4λ

r 401 Contact width 2λ Contact r 401 Polysilicon Contact Metal/Polysilicon Contact

r 404 Extra Poly surrounding contact Contact r 404 Polysilicon Contact Metal/Polysilicon Contact r 404 1λ

r 405 Extra metal surrounding contact Contact Polysilicon Contact Metal/Polysilicon Contact r 405 1λ

r 403 Extra diffusion surrounding contact 1λ r 403 Polysilicon P+ Diff N - Well r 403 Polysilicon N+ Diff

r 501 Between two Metals 4λ Metal 1 Metal 4 r 501 Metal 2 Metal 5 r 501 Metal 3 Metal 6

r 510 Metal 1 Metal 2 Minimum Metal area 16λ 2 r 510 Metal 3 Metal 4 Metal 5 Metal 6 r 510

Step 1: Select Foundary

Step 2: Select Foundary

Step 3: n+ Diffussion

Step 4: Polysilicon

Step 5: n+diff and Metal Contact

• This Completes n. MOS design • Now go for p. MOS Design, and the first need is to construct N Well

Step 6: Create N Well

Step 6: p+ Diffusion

Step 7: Polysilicon

Step 8: Contacts

Final Connections • p. MOS Completed • Now Interconnection of p. MOS and n. MOS to complete inverter • Connect Source of p. MOS to VDD and Source of n. MOS to VSS. • Short the Drain of both p. MOS and n. MOS.

INVERTER: Complete Design

Check DRC

Assign Source • Assign Signal (Clock) to Gate Terminal • Add Visible node at Output

Inverter with Source

Run Simulation

VTC Characteristics

Thanks Give Your Feedbacks at: www. amitdegada. weebly. com/blog. html