Lab 09 D Flip Flop Shift Registers and

Lab 09 : D Flip Flop, Shift Registers and Switch Bounce: Slide 2 The D Flip Flop. Slide 3 4 -Bit Shift Register. Slide 4 Switch Bounce. Slide 5 Shift Register De-bounce System: Flip switch from 0 to 1. Slide 6 Shift Register De-bounce System: Flip switch from 1 to 0. Slide 7 Flip Flop De-bounce System: Use with older IC technology.

Lab 09 : The D Flip Flop : The D flip flop is used to store binary Data. The logic level at the “D” (data) input is transferred to the Q output when the clock is asserted. It remains stored at output Q until the clock is asserted a second time. That’s it … simple! 1 0 D Q >Clk Q 1 0 If look inside the D flip flop you can see how it works. Let’s assume the initial conditions at Q are 0. 1 0 D 1 0 0 1 S Q >Clk R Q 1 0 0 1 Set D to logic 1. Show the logic levels at S and R The internal SR inputs are in the set mode. The flip flop will set if D=1 and the clock is asserted. Q = D! Set D to logic 0. The internal SR inputs are in the reset mode. The flip flop will reset if D=0 and the clock is asserted. Q = D again! Slide #2

Lab 09 : 4 -Bit Shift Register : The 4 -bit shift register can shift data from QA to QB to QC to QD. The shift register will be filled with 1’s then it will be filled with 0’s. Assume the initial conditions are : Qa=Qb=Qc=Qd=0. Din is the input to QA. The data at QA shifts to QB. The data at QB shifts to QC. QC shifts to QD. Apply a logic 1 at input Din and clock the shift register 4 times. You have seen how it takes 4 clock pulses to fill the shift register with 1’s. Din will now be connected to logic 0. This will shift the 1’s out and fill the shift register with 0’s. 4 Bit Shift Register 1 1 0 Qa Din Qb >Clk Qc Qd 1 0 1 0

Lab 09 : Switch Bounce: Switch bounce is generated each time a switch is flipped. Switch bounce does not cause any lasting errors in the operation of AND/OR gate systems. Switch bounce can cause errors in the operation of Flip Flop systems. A switch is a mechanical device that closes contacts. SWITCH BOUNCE occurs when a switch is flipped and its contacts are moved from 0 to 1 or 1 to 0. The contacts chatter causing a small electrical storm that lasts about 20 milliseconds. 5 v 1 0 Switch bounce generates several +ve edge and -ve edge signal transitions during this 20 milli. Sec time interval. These additional transitions can clock a flip flop several times. 20 milli. Sec. Logic gate systems respond erratically while switch bounce is occurring. After 20 milli. Sec switch bounce dissipates and the logic gate system responds predictably. No lasting problems Slide #4

Lab 09 : Shift Register De-bounce System: Flip switch from 0 to 1. The 4 -bit shift register will be used to eliminate switch bounce. The switch will be flipped from 0 to 1. Assume the initial conditions are : Switch = 0 and Qa=Qb=Qc=Qd=0. Every 5 milliseconds a positive edge on the clock shifts another 0 into Qa. This 0 is shifted down to Qb, Qc, Qd. The continuous flow of 0’s through the shift register keeps all AND gate inputs low. Case 1: Flip the switch to 1 with No switch bounce: It takes (4 x 5) 20 milliseconds to fill the shift register with 1’s. The AND gate is 1 after 20 milliseconds. Case 2: Flip the switch to 1 with switch bounce: Re-start with the switch at 0. Flip the switch to 1. The switch bounces Din from 1 to 0 to 1 several times in 20 milliseconds. The animation will show you the response to the switch bounce. The AND gate output changes to 1 once the bounce has settled. Flip the switch 20 milli. Sec. 1 5 v 4 Bit Shift Register Qa 01 1 0 0 0 1 Din Qb >Clk Qc 1 0 1 0 Qd 0 1 Pulse every 5 milli. Secs. After 28 milliseconds the AND gate outputs a single positive edge. The bounce is eliminated. 0 1

Lab 09 : Shift Register De-bounce System: Flip switch from 1 to 0. The 4 -bit shift register will be used to eliminate switch bounce. The switch will be flipped from 1 to 0. Assume the initial conditions are : Switch = 1 and Qa=Qb=Qc=Qd=1. Every 5 milliseconds a positive edge on the clock shifts another 1 into Qa. This 1 is shifted down to Qb, Qc, Qd. The continuous flow of 1’s through the shift register keeps all AND gate inputs high. Flip the switch to 0 with switch bounce: Start with the switch at 1. Flip the switch to 0. The switch bounces Din from 0 to 1 to 0 several times in 20 milliseconds. The animation will show you the response to the switch bounce. The AND gate output changes to 0 when Qa=0. Flip the switch 20 milli. Sec. 1 5 v 4 Bit Shift Register Qa 10 0 1 Din Qb >Clk Qc 1 0 1 0 Qd 0 1 Pulse every 5 milli. Secs. After 28 milliseconds the bounce is eliminated. The AND gate changes to a 0, once, at the beginning of the bounce interval. 1 0

Lab 09 : Flip Flop De-bounce System: An SC flip flop can eliminate the effect of switch bounce. This circuit is used in many older IC technology systems. 5 V Pulse 5 V 5 V 4. 7 K 0 1 1 S Q Q R 0 1 150 1 0 0 The initial conditions are S=0 and R=1. The spring detent switch is in the up position (not pressed). The cross coupled NAND gates create a flip flop with active low inputs. The flip flop SETs Q. This keeps the LED off. Flipping the switch makes S=1 and creates switch bounce at input R. When R=0 it resets the Q output of the flip flop and turns on the LED. When R=1 it puts the FF in the “HOLD” mode and Q stays at 0 and keeps the LED on. The bounce continues with 3 more changes from 0 to 1 to 0. These transitions do not change the output of the circuit. They repeat the RESET, HOLD, RESET cycle. The output of the circuit generates one clean pulse without any bounce. Slide #7 When the switch is released it springs back to the SET position. The switch bounce is now on the SET input. It causes the flip flop to cycle between the SET mode and the HOLD mode. This completes the pulse at the output and turns off the LED. The switch has been eliminated.