L 7 Sequential Building Blocks Flipflops Latches and

L 7: Sequential Building Blocks (Flip-flops, Latches and Registers) Acknowledgements: Materials in this lecture are courtesy of the following sources and are used with permission. Prof. Randy Katz (Unified Microelectronics Corporation Distinguished Professor in Electrical Engineering and Computer Science at the University of California, Berkeley) and Prof. Gaetano Borriello (University of Washington Department of Computer Science & Engineering) from Chapter 2 of R. Katz, G. Borriello. Contemporary Logic Design. 2 nd ed. Prentice-Hall/Pearson Education, 2005. J. Rabaey, A. Chandrakasan, B. Nikolic. Digital Integrated Circuits: A Design Perspective. Prentice Hall/Pearson, 2003. Introductory Digital Systems Laboratory 1

Combinational Logic Review in 0 in 1 Combinational Circuit in. M-1 in. N-1 Combinational logic circuits are memoryless No feedback in combinational logic circuits Output assumes the function implemented by the logic network, assuming that the switching transients have settled Outputs can have multiple logical transitions before settling to the correct value Introductory Digital Systems Laboratory 2

A Sequential System Inputs Outputs COMBINATIONAL LOGIC Current State Registers Q Next state D Memory element CLK Sequential circuits have memory (i. e. , remember the past) The current state is “held” in memory and the next state is computed based the current state and the current inputs In a synchronous systems, the clock signal orchestrates the sequence of events Introductory Digital Systems Laboratory 3

A Simple Example Adding N inputs (N-1 Adders) in 0 in 1 in 2 in. N-1 Using a sequential (serial) approach reset in DQ Current_Sum clk Introductory Digital Systems Laboratory 4

Implementing State: Bi-stability Vo 1 =Vi 2 = Vo 1 Point C is Metastable Vo 2 = Vi 1 C Vi 2 Vo 1 V i 1 V o 2 Vi 1 = Vo 2 A Points A and B are stable (represent 0 & 1) V i 2 = Vo 1 A V i 2 = V o 1 C B B V i 1 = V o 2 Introductory Digital Systems Laboratory Vi 1 = V o 2 5

NOR-based Set-Reset (SR) Flipflop SR = 00, 10 SR = 00, 01 S Q R Q S SR = 1 0 Q Q R Reset S R Q Q 0 0 Q Q 1 0 0 1 1 1 0 0 1 0 SR = 0 1 SR = 1 0 SR = 11 Set SR = 1 1 QQ 00 Forbidden State Hold QQ 10 QQ 01 SR = 0 0 Reset Set R S Q ? ? Q Flip-flop refers to a bi-stable element (edge-triggered registers are also called flip-flops) – this circuit is not clocked and outputs change “asynchronously” with the inputs L 4: 6. 111 Spring 2006 Introductory Digital Systems Laboratory 6

Making a Clocked Memory Element: Positive D-Latch D Q S CLK R hold D Q sample hold R and S G clock clk A Positive D-Latch: Passes input D to output Q when CLK is high and holds state when clock is low (i. e. , ignores input D) A Latch is level-sensitive: invert clock for a negative latch Introductory Digital Systems Laboratory 7

Multiplexor Based Positive & Negative Latch 2: 1 multiplexor in 0 0 in 1 1 Positive Latch Negative Latch out 0 D Q 1 1 D Q 0 SEL Out = sel * in 1 + sel * in 0 CLK clk "data" "remember" "load" "stored value" Introductory Digital Systems Laboratory 8

74 HC 75 (Positive Latch) 2 1 D 13 LE 1 -2 D Q 1 Q 16 1 Q 1 2 Q 15 2 Q 14 CP Q L 1 3 2 D D Q Inputs Outputs Operating Modes CP Q LEn-n n. D n. Q L 2 6 3 D 4 LE 3 -4 D Q 3 Q 10 3 Q 11 4 Q 9 4 Q 8 CP Q H L L H H L L X q q Data Enabled Data Latched L 3 7 4 D D Q CP Q Figures by MIT Open. Course. Ware. L 4 Introductory Digital Systems Laboratory 9

Building an Edge-Triggered Register Negative latch D D Q Positive latch QM G D Q D Q Q G CLK Slave Master CLK 0 1 D 0 QM 1 Q D QM Q CLK Master-Slave Register Image by MIT Open. Course. Ware. Use negative clock phase to latch inputs into first latch Use positive clock to change outputs with second latch View pair as one basic unit master-slave flip-flop twice as much logic Introductory Digital Systems Laboratory 10

Latches vs. Edge-Triggered Register Edge triggered device sample inputs on the event edge 7474 D Q Transparent latches sample inputs as long as the clock is asserted Timing Diagram: Clk Positive edge-triggered register D 7475 D Clk Q C Clk Level-sensitive latch Bubble here for negative edge triggered register Q 7474 Q 7475 Behavior the same unless input changes while the clock is high Introductory Digital Systems Laboratory 11

Important Timing Parameters Clock: Periodic Event, causes state of memory element to change Clock Tsu Th memory element can be updated on the: rising edge, falling edge, high level, low level Input There is is aa timing "window" aroundthe clocking event during which the input must remain stable and unchanged in in order to to be be recognized Setup Time (Tsu) Minimum time before the clocking event by which the input must be stable Hold Time (Th) Minimum time after the clocking event during which the input must remain stable Propagation Delay (Tcq for an edge-triggered register and Tdq for a latch) Delay overhead of the memory element Introductory Digital Systems Laboratory 12

The J-K Flip-Flop J K S R Q Q 100 J J K Q+ Q+ 0 0 Q Q 0 1 0 1 1 Q Q K Q Q Eliminate the forbidden state of the SR Flip-flop Use output feedback to guarantee that R and S are never both one Introductory Digital Systems Laboratory 13

J-K Master-Slave Register Sample inputs while clock low Sample inputs while clock high J S Q R K CLK Q Set P P Reset 1's Catch Toggle J K Q R Q 100 Clk P Master outputs P Q Q Correct Toggle Operation K J S Q Slave outputs Q Is there a problem with this circuit? Introductory Digital Systems Laboratory 14

Pulse Based Edge-Triggered J-K Register Input X Input Output X tp. LH Schematic Output J K S Q R Q J Q K Q JK Register Logic Symbol JK Register Schematic Introductory Digital Systems Laboratory 15

Pulse-Triggered Registers Ways to design an edge-triggered sequential cell: Master-Slave Latches Data L 1 L 2 D Q Clk Pulse-Based Register Data Clk Latch D Q Clk Short pulse around clock edge Pulse registers are widely used in high-performance microprocessor chips (Sun Microsystems, AMD, Intel, etc. ) The can have a negative setup time! Introductory Digital Systems Laboratory 17

D Flip-Flop vs. Toggle Flip-Flop 1 D Q D Flip-Flop 0 Clk D QN 0 0 1 1 1 0 0 1 T Q T (Toggle) Flip-Flop 0 Clk T QN 0 Q N-1 1 QN-1 0 1 Introductory Digital Systems Laboratory 16

Realizing Different Types of Memory Elements Characteristic Equations D: Q+ = D J-K: Q+ = J Q + K Q T: Q+ = T Q + T Q E. g. , J=K=0, then Q+ = Q J=1, K=0, then Q+ = 1 J=0, K=1, then Q+ = 0 J=1, K=1, then Q+ = Q Implementing One FF in Terms of Another D J Q C K Q Q K D Q J D implemented with J-K C Q J-K implemented with D Introductory Digital Systems Laboratory 17

Design Procedure Excitation Tables: What are the necessary inputs to cause a particular kind of change in state? Q Q+ 0 0 0 1 1 J K 0 X 1 X 0 T 0 1 1 0 D 0 1 D Implementing D FF with a J-K FF: Q 0 1 1) Start with K-map of Q+ = ƒ(D, Q) 0 0 1 2) Create K-maps for J and K with same inputs (D, Q) 1 0 1 3) Fill in K-maps with appropriate values for J and K to cause the same state changes as in the original K-map D 0 1 0 0 1 1 X X Q E. g. , D = Q= 0, Q+ = 0 then J = 0, K = X J =D D 0 1 0 X X 1 1 0 Q Q+ = D K=D Introductory Digital Systems Laboratory 18

Design Procedure (cont. ) Implementing J-K FF with a D FF: 1) K-Map of Q+ = F(J, K, Q) 2, 3) Revised K-map using D's excitation table its the same! that is why design procedure with D FF is simple! JK Q 0 1 J 00 01 11 10 0 0 1 1 1 0 0 1 K Q+ = D = JQ + KQ Resulting equation is the combinational logic input to D to cause same behavior as J-K FF. Of course it is identical to the characteristic equation for a J-K FF. Introductory Digital Systems Laboratory 19

System Timing Parameters In D Q Combinational Logic D Q Clk Register Timing Parameters Tcq : worst case rising edge clock to q delay Tcq, cd: contamination or minimum delay from clock to q Tsu: setup time Th: hold time Logic Timing Parameters Tlogic : worst case delay through the combinational logic network Tlogic, cd: contamination or minimum delay through logic network Introductory Digital Systems Laboratory 20

System Timing (I): Minimum Period CLout In Combinational Logic D Q Clk CLK Th Th IN Tsu Tcq cq FF 1 Tcq, cd Tlogic Tcq, cd CLout Tl, cd Tsu 2 T > Tcq + Tlogic + Tsu Introductory Digital Systems Laboratory 21

System Timing (II): Minimum Delay CLout In Combinational Logic D Q Clk CLK Th Th IN Tsu FF 1 Tcq, cd CLout Tl, cd Tcq, cd + Tlogic, cd > Thold Introductory Digital Systems Laboratory 22

Shift-Register Typical parameters for Positive edge-triggered D Register D Tsu Th 20 ns 5 ns CLK Th 5 ns all measurements are made from the clocking event that is, the rising edge of the clock Tw 25 ns Tplh 25 ns 13 ns Q Tsu 20 ns Tphl 40 ns 25 ns Shift-register IN DQ Q 0 DQ Q 1 100 OUT IN Q 0 Q 1 CLK Introductory Digital Systems Laboratory 23