L 25 Final Review AU 15 Final Exam

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L 25 – Final Review AU 15 Final Exam – Classroom – Journalism 300

L 25 – Final Review AU 15 Final Exam – Classroom – Journalism 300 (in class) Wednesday Dec 14 th – 2: 00 pm-3: 45 pm

Topics o In class exam n n There may be a question on the

Topics o In class exam n n There may be a question on the traditional manual sequential machine methodology. This most likely would be to work out the state diagram of some sequence detector or straightforward state machine. Much like the midterm. 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne De. Groat, ECE, OSU 2

The course listing o Design and analysis of sequential circuits; digital circuit design using

The course listing o Design and analysis of sequential circuits; digital circuit design using building blocks, programmable logic devices; design of basic computer components such as arithmetic logic units 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne De. Groat, ECE, OSU 3

Spring 15 topic on the exam o o Besides state diagram knowledge and possible

Spring 15 topic on the exam o o Besides state diagram knowledge and possible question. Questions on the Micro. Baby architecture. Questions on the Micro. Baby datapath and ALU. Questions on the operation of Micro. Baby 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne De. Groat, ECE, OSU 4

HDL topics o o The VHDL Entity The VHDL Architecture Writing the VHDL description

HDL topics o o The VHDL Entity The VHDL Architecture Writing the VHDL description of a small leaf unit to perform a specified function. Writing a VHDL structural description to integrate several leaf units. 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne De. Groat, ECE, OSU 5

HDL questions o Given a small leaf block specification write the ENTITY and ARCHITECTURE

HDL questions o Given a small leaf block specification write the ENTITY and ARCHITECTURE for it. n o Probably a dataflow requiring one or two logic equations implemented as a concurrent signal assignment statement. Given the ENTITY and ARCHITECTURE name create a structural architecture given a simple diagram. n n Know how to select bits from a bit_vector, i. e. , Having myvec : bit_vector (7 downto 0); o o select the 4 th bit -- myvec(4) Select the 2 nd bit – myvec(2) 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne De. Groat, ECE, OSU 6

More HDL o Know the HDL way to specify state machines n n An

More HDL o Know the HDL way to specify state machines n n An ARCHITECTURE with 3 process The F/F process that latches next_state into state The next_state PROCESS that given a current state and the value of inputs, generates a value for next_state. The output PROCESS that generates the final outputs. o o For a Moore machine this could be as simple as valout <= cur_state; 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne De. Groat, ECE, OSU 7

Almost certainly o Diagram of a sequential machine such as o Given a sequential

Almost certainly o Diagram of a sequential machine such as o Given a sequential machine diagram n n What are next state equations? Construct State Table 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne De. Groat, ECE, OSU 8

Problem continued o Now having state table n n n Create the VHDL description

Problem continued o Now having state table n n n Create the VHDL description with its 3 processes Know if this a Mealy or Moore machine Be able to create the VHDL if the VHDL coding is with symbolic notation for state, or a binary encoding of state. 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne De. Groat, ECE, OSU 9

VHDL o o o Know the basic of ENTITIES and ARCHITECTURES, component use, declarative

VHDL o o o Know the basic of ENTITIES and ARCHITECTURES, component use, declarative regions, scope. You should be able to do leaf unit ENTITY and ARCHITECTURE coding. You should be also to create structural VHDL designs. 9/2/2012 – ECE 3561 Lect 9 Copyright 2012 - Joanne De. Groat, ECE, OSU 10