Kuliah Rangkaian Digital Kuliah 5 Desain Rangkaian Kombinasional

Kuliah Rangkaian Digital Kuliah 5: Desain Rangkaian Kombinasional Teknik Komputer Universitas Gunadarma 1

Topik 5 – Desain Rangkaian Kombinasional Task: Given a description of problem (logical statement), find the corresponding digital circuits that produce the output (answer) given a set of inputs (condition). Contoh-2: n n Parking lot controller Elevator controller Prime number indicator Adder, subtractor, … 2

Brute-force approach Design: given a description or truth table, find the corresponding Boolean expression and digital circuit. Brute-force design methodology: n n n Truth table canonical sum So. P or sum of minterms AND-OR / NAND-NAND Example: prime number detector F = SN 3 N 2 N 1 N 0(1, 2, 3, 5, 7, 11, 13) Row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 N 3 N 2 N 1 N 0 0 0 0 1 1 0 0 0 1 0 1 1 0 0 0 1 1 0 0 1 1 1 1 0 1 1 F 0 1 1 1 0 1 0 0 3

Minterm list -> canonical sum 4

Algebraic simplification Recall (T 8) X · Y + X · Y’ = X Simplify equation to reduce number of gates & gate inputs 5

Resulting circuit 6

Combinational circuit design/minimization Objective: n n Minimizing # logic gates Minimizing # inputs to the logic gates Note different logic gates may have different # transistors General idea: simplify the Boolean expression using theorems, especially (T 10, T 10’, T 13’) Karnaugh-map (K-map) n n n Graphical representation of the truth table Offers visualization of (T 10, T 10’) Works for functions with less than 6 variables Real world: use programs to minimize logic circuits n E. g. , VHDL, Verilog, ABEL, … 7

Karnaugh-map usage Plot 1 s corresponding to minterms of function. Circle largest possible rectangular sets of 1 s. n n # of 1 s in set must be power of 2 OK to cross edges Read off product terms, one per circled set. n n n Variable is 1 include variable Variable is 0 include complement of variable Variable is both 0 and 1 variable not included Circled sets and corresponding product terms are called `prime implicants’ Minimum number of gates and gate inputs 8

3 variable example: F = S(1, 2, 5, 7) Rules of thumb: n n n Group (prime implicant) as large (many 1 s) as possible As few groups as possible Overlaps are OK 9

4 variable K-map example Note how it maps to the rows of the truth table 10

Prime-number detector revisited 11

Compare with the previous circuit When we solved algebraically, we missed one simplification- the circuit below has three less gate inputs. 12

Design example: alarm controller Problem statement: n n The ALARM output is 1 if PANIC is 1, or if ENABLE is 1 and the house is not secure. The house is secure if WINDOW, DOOR, GARAGE are all 1 This can be put in logic expressions as follows: ALARM = PANIC + ENABLE · SECURE’ SECURE = WINDOW · DOOR · GARAGE ALARM = PANIC + ENABLE · (WINDOW · DOOR · GARAGE)’ Multiply out and use (T 13), we get the So. P form ALARM = PANIC + ENABLE · WINDOW’ + ENABLE · DOOR’+ ENABLE · GARAGE’ 13

K-map with don’t-cares In some cases, the output of a combinational circuit doesn’t matter for certain input combinations. Such combinations are called don’t-cares and the output is represented in the truth table and K-maps as `d’. When using K-maps to minimize such functions: n n Allow d’s to be included when grouping sets of 1’s to make the sets as large as possible. Do not circle any set that only contains d’s. 14

Example with don’t-cares n Prime number detection for BCD numbers (takes value between 0 -9) – minterms 10 -15 are treated as don’t-cares: F(N 3, N 2, N 1, N 0) = S N 3, N 2, N 1, N 0 (1, 2, 3, 5, 7) + d(10, 11, 12, 13, 14, 15) From K-map: N 3 N 2 Prime Implicants: N 3’· N 0 N 2’· N 1 00 Distinguished 1 -cells: Cell 1 covered by N 3’· N 0 Cell 2 covered by N 2’· N 1 Here not all prime implicants are essential prime implicants that must be included minimum SOP expression: F = N 3’ · N 0 + N 2’ · N 1 00 N 1 N 0 N 2 · N 0 01 11 N 1 10 N 3’· N 0 0 1 3 2 1 1 1 01 11 4 12 5 13 7 6 10 N 2 · N 0 8 d 1 1 15 d N 0 d 14 d N 2 9 11 d 10 d N 2’· N 1 15

5 -variable K-maps The K-map for a 5 -variable logic function is organized as two 4 -variable K-maps: n Can be visualised as being one 4 -variable map on top of another 4 -variable map W W WX WX 00 YZ 00 01 Y 11 01 11 10 0 4 12 8 1 5 13 9 3 7 15 11 2 14 6 10 10 00 YZ 00 01 Z Y 11 01 11 10 16 20 28 24 17 21 29 25 19 23 31 27 18 22 30 26 Z 10 X V=1 16

5 -variable K-map example F(V, W, X, Y, Z) = S V, W, X, Y, Z(4, 5, 6, 7, 9, 11, 13, 15, 27, 29, 31) W W WX WX 00 YZ 00 01 Y 11 10 01 0 4 1 5 3 7 2 6 11 1 1 12 8 13 9 1 15 1 14 1 10 1 00 YZ 00 1 11 10 1 01 Z Y 11 01 11 10 16 20 28 24 17 21 29 25 19 23 31 27 18 22 30 1 1 1 Z 1 26 10 X V=1 17

5 -variable K-map example – cont. W W WX WX 00 YZ 00 0 4 1 5 01 Y 01 11 3 2 10 7 6 11 1 1 12 8 13 9 1 15 1 14 1 10 1 00 1 11 01 Z 1 Y 10 11 01 11 10 16 20 28 24 17 21 29 25 19 23 31 27 18 22 30 1 1 1 Z 1 26 10 X V’ · W’· X 00 YZ V=0 X W·Z V=1 Minimum SOP: F = V’ · W’· X + W · Z 18

K-map product-of-sum minimization Using K-map, find a minimal Po. S expression for F(X, Y, Z) = P X, Y, Z (0, 3, 4, 7) Truth Table Row 0 1 2 3 4 5 6 7 X 0 0 1 1 Y 0 0 1 1 Z 0 1 0 1 X F 0 1 1 0 XY 00 Z 0 0 1 1 0 01 11 10 2 6 4 3 7 5 0 0 0 Z Y 19

K-map Po. S minimization – cont. (Y + Z) X XY 00 Z 0 0 Truth Table Row 0 1 2 3 4 5 6 7 X 0 0 1 1 Y 0 0 1 1 Z 0 1 0 1 F 0 1 1 0 1 01 11 6 2 10 4 0 0 1 3 0 7 0 5 Z Y (Y’ + Z’) Minimum Po. S: F = (Y + Z) · (Y’ + Z’) 20

K-map Po. S minimization – another example Using K-map, find a minimal POS expression for F(W, X, Y, Z) = P W, X, Y, Z (1, 3, 8, 10, 12, 13, 14, 15) W WX 00 YZ 00 01 11 Y 10 01 11 0 4 12 1 5 13 7 15 6 14 3 2 0 0 0 10 8 9 Z 11 10 0 X 21

K-map Po. S minimization – another example W WX 00 YZ 00 01 (W + X + Z’) 11 Y 10 01 11 0 4 12 1 5 13 7 15 6 14 3 2 0 0 0 10 8 0 9 Z 11 10 0 (W’ + Z) 0 (W’ + X’) X Minimum POS: F = (W + X + Z’) · (W’ + Z) · (W’ + X’) 22

Combinational Circuit: Transient vs. Steady-state Output Timing Diagram X X X’ 1 0 X’ propagation delay 1 Time 0 1 0 Transient output Steady-state output Transient output: the temporary output due to the gate propagation delay(s) n Gate propagation delay: the time it takes to pull up (or down) the output signals due to the change at the input – depends on the transistor level implementation. 23

Hazards in combinational circuits Output glitch: a momentary (transient) fluctuation in output signal due to changes in input signal. 1 0 1 1 0 Static-0 Hazard 0 Static-1 Hazard 1 0 Dynamic Hazard Example Static hazards: n n Static-0 hazard: The output should be 0 but goes momentary to 1 as a result of an input change – possible in AND-OR circuits Static-1 hazard: The output should be 1 but goes momentary to 0 as a result of an input change – possible in OR-AND circuits Dynamic hazards: The output changes more than once as a result of a single input change (impossible in 2 -level circuits). 24

Example: static-1 hazard A static-1 hazard exists in the following AND-OR circuit when X=1, Y=1 and Z changes from 1 to 0 (assume all gates have propagation delay D) Extra propagation delay between Z and Z’ Circuit X 1 X · Z’ Z’ Z 1 0 1 0 1 1 0 Timing Diagram Z 1 0 Z’ 1 0 F 1 0 Y 1 K-map Y·Z 1 0 X·Z’ 1 0 X XY 00 Z 0 1 01 11 0 2 6 1 3 7 1 Y 1 1 10 4 1 5 X · Z’ Z Y·Z F 1 0 D D D Steady-state output Time 25

Eliminate static-1 hazard using K-map Static-1 hazards are found using k-maps by finding adjacent 1 cells that are covered by different product terms. To eliminate static-1 hazards, additional product terms (prime implicants) are needed to cover such cells thus covering the transition of the variable causing the hazard. For the previous example the static-1 hazard is eliminated by including the additional product term X · Y New F = X · Z’ + Y · Z + X · Y X X·Y 00 Z 0 0 1 Y·Z 1 01 11 6 2 3 X 7 1 Y 1 1 10 4 1 5 X·Z’ Z Z’ X · Z’ X·Y F Z X·Y Y Y·Z 26

Eliminate static-0 hazard using K-map A static-0 hazard occurs in OR-AND circuits when an input variable and its complement are connected to two different OR gates. The procedure to find and eliminate static-0 hazards using Kmaps is done in a dual way to finding static-1 hazards. Static-0 hazards are found using k-maps by finding adjacent 0 cells that are covered by different sum terms. To eliminate static-0 hazards, additional sum terms (prime implicates) are needed to cover such cells thus covering the transition of the variable causing the hazard. 27

Homework #2 Turn in: (show your steps) n n n n 4. 13 (f), 4. 14 (f) 4. 19 (e), 4. 20 (e), 4. 21 (e) 4. 22 (d) 4. 45 4. 47 (refer to 4. 46 for hints) 4. 55 (a) (b) (c) 4. 65 4. 72 (f), 4. 73 (f) Self exercise: (you do not need to turn in these, but think about them!!) n 4. 48, 4. 50, 4. 52, 4. 68, 4. 71, 4. 84, 4. 85 28