King Fahd University of Petroleum and Minerals College

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King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer Engineering Department COE 308 MIPS Instructions COE 308 MIPS Architecture 1

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer Engineering Department MIPS Microprocessor without Interlocked Pipeline Stages • RISC microprocessor architecture developed by MIPS Computer Systems Inc. • MIPS designs are used in SGI's computer product line, and have found broad application in embedded systems, Windows CE devices, and Cisco routers. • The Nintendo 64 console, Sony Playstation 2 console, and Sony Playstation Portable handheld system use MIPS processors. • By the late 1990 s it was estimated that one in three RISC chips produced were MIPS-based designs. COE 308 MIPS Architecture 2

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer Engineering Department Instructions in MIPS • Reduced Instruction Set • 3 Operands per operation: 2 sources and 1 destination • Most instructions are of the form: Operation dst, src 1, src 2 Where it means: dst src 1 Operation src 2 Example: addition add dst, src 1, src 2 means: dst src 1 + src 2 COE 308 MIPS Architecture 3

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer Engineering Department Operands • 32 General-purpose registers: R 0 – R 31 – R 0 is “wired” to the value “ 0” – Writing to R 0 does not change its value • Special-purpose registers LO and HI – Hold results of integer multiply and divide • Special-purpose program counter PC • 32 Floating Point Registers (FPRs) – Floating Point Unit (FPU) can be either 32 -bit or 64 -bit – FPRs are 32 bits on a 32 -bit FPU, and 64 bits on a 64 -bit FPU • Almost all instructions operate on registers • All destination operands are registers • One of the source operands is a signed/unsigned 16 -bits immediate value COE 308 MIPS Architecture 4

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer Engineering Department Instruction Format • Fixed Format • 3 Format Types – Register: R-type – Immediate: I-type – PC-relative: J-type 6 bits 5 bits 6 bits All MIPS Instructions Format COE 308 MIPS Architecture 5

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer Engineering Department R-Type op 6 bits rs rt rd shamt funct 5 bits 6 bits • Used by – Arithmetic Instructions – Logic Instructions – Except when Immediate Addressing mode used COE 308 MIPS Architecture 6

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer Engineering Department I-Type op 6 bits rs rt address/immediate 5 bits 16 bits • Used by – Instructions using Immediate addressing mode – Instructions using Displacement addressing mode – Branch instructions COE 308 MIPS Architecture 7

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer Engineering Department J-Type op target address 6 bits 26 bits • Used by – Jump Instructions COE 308 MIPS Architecture 8

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer Engineering Department Instructions • • Arithmetic and Logic Instructions Comparison Instructions Load/Store and Data Movement Instructions Branch and Jump Instructions COE 308 MIPS Architecture 9

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer Engineering Department Arithmetic & Logic Instructions small circle in front of the instruction means that it is a pseudo-instruction COE 308 MIPS Architecture 10

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer Engineering Department Addressing Modes The second operand of all of the load and store instructions must be an address. The MIPS architecture supports the following addressing modes: COE 308 MIPS Architecture 11

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer Engineering Department Load Instructions COE 308 MIPS Architecture 12

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer Engineering Department Store Instructions COE 308 MIPS Architecture 13

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer Engineering Department Data Movements Instructions The data movement instructions move data among registers. Special instructions are provided to move data in and out of special registers such as hi and lo. COE 308 MIPS Architecture 14

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer Engineering Department Exceptions COE 308 MIPS Architecture 15

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer Engineering Department Assembly Conventions COE 308 MIPS Architecture 16

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer Engineering Department Comments, Labels, Registers and Directives • Comment: – “#”: • Label: – <label: > • Registers – $<register_number> or $<register_label> • Directives – – – . data: for defining the constant segment. text: for defining the code. ascii: for defining strings. asciiz: for defining zero-terminated strings. byte: for defining constants COE 308 MIPS Architecture 17

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer Engineering Department Registers Even though any of the registers can theoretically be used for any purpose, MIPS programmers have agreed upon a set of guidelines that specify how each of the registers should be used. Programmers (and compilers) know that as long as they follow these guidelines, their code will work properly with other MIPS code. COE 308 MIPS Architecture 18

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer

King Fahd University of Petroleum and Minerals College of Computer Science And Engineering Computer Engineering Department SPIM Simulator Source code: text file saved as with “. asm” extension. COE 308 MIPS Architecture 19