Kahn Process Networks Static Multirate Dataflow Dynamic Multirate

Возможности по моделированию • Kahn Process Networks • Static Multi-rate Dataflow • Dynamic Multi-rate

Platform Architect от Synopsys • Traffic Generators – Generic File Reader Bus Master (GFRBM)

Продолжение – Generic approximately-timed System. C TLM bus libraries for industry-standard IEEE 1666 -2011

Продолжение • Memory Subsystem Models – Generic approximately-timed System. C TLM memory subsystem models

Продолжение • Processor Models – Cycle-accurate System. C TLM processor support packages (PSPs) are

Ссылки по System. C http: //www. asicworld. com/systemc/tutorial. html http: //accellera. org/downloads/standards/ ieee -

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Возможности по моделированию • Kahn Process Networks • Static Multi-rate Dataflow • Dynamic Multi-rate Dataflow • Communicating Sequential Processes • Discrete Event as used for – RTL hardware modeling – Network modeling (e. g. stochastic or “waiting room” models) – Transaction-based So. C platform modeling

Слои System. C

Platform Architect от Synopsys • Traffic Generators – Generic File Reader Bus Master (GFRBM) for trace-driven traffic generation – Generic Virtual Processing Unit (VPU) for application task-mapping and task-driven traffic generation • Interconnect Models – Cycle-accurate System. C TLM bus libraries for ARM AMBA® 2 AHB™/APB™, AMBA 3 AXI™, and AMBA 4 AXI™ protocols 18

Продолжение – Generic approximately-timed System. C TLM bus libraries for industry-standard IEEE 1666 -2011 System. C TLM-2. 0 protocols, plus support for the approximately-timed models available from Arteris® for the Arteris Flex. No. C™ Network on Chip (No. C) interconnect, which provide on-chip connectivity for AMBA® AXI™, AHB -Lite, APB™, and PIF protocols. 19

Продолжение • Memory Subsystem Models – Generic approximately-timed System. C TLM memory subsystem models for ARM AXI and IEEE-1666 2011 System. C TLM-2. 0 interfaces, including the Synopsys Design. Ware Enhanced Universal DDR Memory Controller (u. MCTL 2) – Cycle-accurate memory subsystem models are available for Platform Architect through HDL co-simulation with user-provided, third -party and Synopsys RTL memory controller IP 20

Продолжение • Processor Models – Cycle-accurate System. C TLM processor support packages (PSPs) are available for Tensilica and MIPS processor families, and through HDL co-simulation with userprovided RTL for ARM processor families. 21

Ссылки по System. C http: //www. asicworld. com/systemc/tutorial. html http: //accellera. org/downloads/standards/ ieee - бесплатно доступные стандарты IEEE в части System. C http: //www. ece. iastate. edu/~zambreno/cl asses/cpre 588/documents/Ros. Swa 05 A. pdf 22