July 11 2016 Efficient Combinational Circuits for Division

July 11, 2016 Efficient Combinational Circuits for Division by Small Integer Constants H. Fatih Uğurdağ Vecdi Emre Levent Özyeğin University Istanbul, Turkey Anıl Bayram Dialog Semiconductor Istanbul, Turkey Sezer Gören Yeditepe University Istanbul, Turkey fatih. ugurdag@ozyegin. edu. tr Yeditepe University /22

July 11, 2016 Outline Ø Introduction • Problem Definition • In a Nutshell • Motivation Ø Previous Work Ø Proposed Solution Ø Synthesis Results Ø Conclusions and Future Work fatih. ugurdag@ozyegin. edu. tr Yeditepe University /22

July 11, 2016 Introduction Problem Definition X n Ø Provided the circuit is: Combinational (i. e. Parallel) Divide by Constant d circuit Ø Minimize: Timing (Latency) n–r+1 r Q fatih. ugurdag@ozyegin. edu. tr R with (if possible) good: • Area-Timing Product (ATP) Yeditepe University /22

July 11, 2016 Introduction In a Nutshell Ø wrote a Verilog generator for our proposed architecture (BTCD) parameters: d and n Ø generated 20 circuits each for BTCD and competition for permutations of d = 3, 5, 11, 23 n = 8, 16, 32, 64, 128 Ø and the results are: fatih. ugurdag@ozyegin. edu. tr BTCD Recip. TBCD Timing 1 1. 13 1. 87 Area 1 2. 88 0. 80 ATP 1 3. 01 1. 64 Yeditepe University /22

July 11, 2016 Introduction Motivation Ø Memory Packing Ø Base Conversion Ø Single Dim. to Multi Dim. Conversion fatih. ugurdag@ozyegin. edu. tr Yeditepe University /22

July 11, 2016 Previous Work Ø [5] Jacobsohn, 1973 A combinatoric division algorithm for fixed-integer divisors IEEE Trans. on Computers No hardware discussion, Repeating digits, Correct rounding (2 n log n)/k +4 log k Ø [6] Kozai, 1999 Constant divider US Patent Recursive, Rough hardware discussion 5(log n +log(k+log n)+log(k+log n))+2) Ø [4] Dinechin and Didier, 2012 (TBCD) Table-based division by small integer constants Int. Symp. Applied Reconfigurable Computing (ARC) n(1+r/k) Ø [2] Drane, Cheung, and Constantinides, 2012 (Recip. ) Correctly rounded constant integer division via multiply-add Int. Symp. Circuits and Systems (ISCAS) No remainder log n fatih. ugurdag@ozyegin. edu. tr Yeditepe University /22

July 11, 2016 Related Work Table Based Constant Division (TBCD) X= fatih. ugurdag@ozyegin. edu. tr Yeditepe University /22

July 11, 2016 Related Work Table Based Constant Division (TBCD) – cont’d fatih. ugurdag@ozyegin. edu. tr Yeditepe University /22

July 11, 2016 Related Work Table Based Constant Division (TBCD) – cont’d fatih. ugurdag@ozyegin. edu. tr Yeditepe University /22

July 11, 2016 Related Work Reciprocal based method (Recip. ) Ø Find a and m such that Q = (a. X + a) >> m Ø R = X – d. Q fatih. ugurdag@ozyegin. edu. tr Yeditepe University /22

July 11, 2016 Related Work Kozai’s method FEDBBA 89 = F 0000000 + 0 E 000000 + 00 D 00000 + 000 B 0000 + 0000 B 000 + 00000 A 00 + 00000080 + 00000009 Q 1 + Q 2 + Q 3 + Q 4 + Q 5 + Q 6 + Q 7 + Q 8 = Sum of Qs R 1 + R 2 + R 3 + R 4 + R 5 + R 6 + R 7 + R 8 = Sum of Rs Recurse Sum of Qs fatih. ugurdag@ozyegin. edu. tr Yeditepe University /22

July 11, 2016 Proposed Method Binary Tree based Constant Division (BTCD) X= fatih. ugurdag@ozyegin. edu. tr Yeditepe University /22

July 11, 2016 Proposed Method Binary Tree based Constant Division (BTCD) – cont’d fatih. ugurdag@ozyegin. edu. tr Yeditepe University /22

July 11, 2016 Proposed Method Binary Tree based Constant Division (BTCD) fatih. ugurdag@ozyegin. edu. tr Yeditepe University /22

July 11, 2016 Proposed Method Critical Path 4 i. LUT 1 r. LUT 4 + 5 + 13 + 29 fatih. ugurdag@ozyegin. edu. tr Yeditepe University /22

July 11, 2016 Synthesis Results Experimental Setup Ø Synopsys Design Compiler (DC) TSMC 180 nm worst-case (slow) standard-cell library with a wire-load model Ø Verification Script Ø Synthesis Script Binary search based, iterative synthesis script written in TCL fatih. ugurdag@ozyegin. edu. tr Yeditepe University /22

July 11, 2016 Synthesis Results fatih. ugurdag@ozyegin. edu. tr Yeditepe University /22

July 11, 2016 Synthesis Results – cont’d fatih. ugurdag@ozyegin. edu. tr Yeditepe University /22

July 11, 2016 Conclusions Ø We have proposed a fast but yet area efficient circuit topology (BTCD) for constant division with quotient and remainder output Ø We wrote code generators • that produce RTL and self-checking testbench code • for BTCD as well as competitive existing circuit topologies Ø We automated • design, • verification, • synthesis, and • extraction of the area/timing results via batch scripts fatih. ugurdag@ozyegin. edu. tr Yeditepe University /22

July 11, 2016 Conclusions Ø generated 20 circuits each for BTCD and competition for permutations of d = 3, 5, 11, 23 n = 8, 16, 32, 64, 128 Ø and the results are: fatih. ugurdag@ozyegin. edu. tr BTCD Recip. TBCD Timing 1 1. 13 1. 87 Area 1 2. 88 0. 80 ATP 1 3. 01 1. 64 Yeditepe University /22

July 11, 2016 Future Work Ø Optimize BTCD for non-power of two bitwidths and Optimize the LUTs Ø Optimize Recip. Ø FPGA Synthesis and Comparison to ASIC Synthesis Ø Signed Implementation Ø Wallace Tree for the Additions fatih. ugurdag@ozyegin. edu. tr Yeditepe University /22

July 11, 2016 Thank You fatih. ugurdag@ozyegin. edu. tr Yeditepe University /22