JTAG testing with XJTAG XJTAG Not what you

JTAG testing with XJTAG

XJTAG – Not what you have thought of…

Contents n Main Concepts n System Components n XJTAG Software n Summary – Special Features The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled

Main Concepts n Device centric philosophy n Reactive test pattern generation The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled

The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled The device-centric philosophy n n Tests are written from the perspective of the device being tested, without reference to the circuit. A set of tests written for a device can be used at any time, in any circuit. XJTAG is supplied with a set of ‘device files’, containing tests, so it is possible to create a test system without having to write any test code at all. Any work done in creating tests at an early stage will not be lost, but can easily be modified to form part of a more fully-featured test system later.

The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled Reactive test pattern generation n Using the current state of the board to determine the test patterns that should be generated.

The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled System Components

The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled System Components XJEase Device Files XJInter connect XJEngine XJTAG Project File information required devices to • The testing of non-JTAG Identifies manufacturing create faults a test pattern • Test-Patterns generator • USB to JTAG adapter XJLink • High speed – 480 Mbps • Power supply to low-power target systems Unit Under Test

The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled XJLink

XJLink The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled Connecting the test system to the circuit n n n high-speed JTAG access from any computer with a USB interface. ability to configure the pin mapping between the XJLink and the circuit under test. Standard pin mappings can be selected: n n Multiice Xilinx Altera Byte Blaster alternatively, the pin mapping can be set up to match other specific, non-standard, layouts.

The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled XJEngine

XJEngine n n n High-level, C-like test description language of XJTAG. Used for creating the tests. Used for programing: JTAG devices (CPLDs, FPGAs) n Non-JTAG devices (FLASH) n n The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled Built-in interconnect test.

XJEngine n n The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled Generating the test patterns that implement the device tests. What a test pattern has to achieve in terms of setting pin values is controlled by the device file. The information required to create a test pattern to fulfil that requirement comes from the project file. All of these test patterns are generated as the test system is running. This means that the XJEngine is able to feed the current status of devices in the circuit back to the controlling XJEase device test. This information is used to programmatically control the next test pattern that the XJEngine must generate.

XJEngine (cont. ) The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled Consider the following case: n a device needs to be put into a particular mode to enable testing. n n n XJEase device test simply describes the pins that need. Tests to be driven for thea device are only made for such device to enter the testable mode; by XJTAG’s circuit interaction. The possible test then loops, reading the device state, until a value is read that indicates that the mode has been entered The test can proceed

The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled XJInter connect

XJInterconnect The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled Manufacturing validation n Identifies manufacturing faults: short circuits n open circuits n Stuck-at faults n n proprietary connection test algorithm high percentage of circuit coverage n fault reporting that identifies the exact nature and location of faults n

The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled Example of a situation that causes a major problem for many JTAG connection tests n n n A simple short circuit, such as that shown between nets C and D, can be identified HOWEVER, the inline resistors in nets A and B mean that the short circuit between those two nets would not be detected The XJInterconnection test algorithm overcomes this problem. n When a test inconsistency is identified, more tests are automatically generated to pinpoint the nature and location of that fault.

The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled XJEase Device Files

XJEase Device Files The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled Functional testing of non-JTAG devices n n n The testing of non-JTAG devices is controlled by the 'XJEase device files'. Contain high-level test descriptions for each device being tested. Do not contain any information relating to how those tests should be implemented in the particular circuit under test n Thus all tests developed are re-usable both within and across projects

The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled XJTAG Software

The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled XJAnalyser JTAG chain validation n A powerful graphical tool for: JTAG chain visualization n fast chain validation n circuit debug. n n Checks the integrity of the JTAG chain by extracting the ID code from each device in that chain. n uses the ID codes extracted to identify the appropriate BSDL files from its library.

The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled XJAnalyser - Example information about the pins in a circuit on a per-device basis n A JTAG chain consisting of three devices: n n n Two are normally packaged The third is a BGA device The colours of the pins indicate their current values. XJAnalyser can set the values for output and bi-directional pins to high, low, fast oscillating and slow oscillating XJAnalyser can also display information about the pins in a circuit on a per-device basis or about a selection of pins. n information about the a selection of pins This enables direct access to specific information of interest The main chain window in XJAnalyser

XJRunner n n The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled A run-only environment for XJEase tests. Enabling tests to be run quickly and easily in a production environment.

The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled Summary – Special Features

The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled Summary - Special Features n Pre Design n n Design Validation n XJTAG’s design for test guidelines help to ensure that the eventual design of a circuit will yield the highest possible test coverage for all devices whether or not they comply with the JTAG standard. The process of testing can begin before the first circuit board has been produced XJTAG can produce a design for test report with no hardware attached, to check that the circuit layout provides all of the connections required to implement the specified tests Circuit Testing n XJTAG testing can begin before the circuit (or even the whole JTAG chain) is fully populated

The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled Summary - Special Features n (cont. ) Multiple levels of abstraction n n The core of XJTAG’s device centric philosophy Test systems can be developed very quickly: n n Tests are created by simply describing the pins that need to be set and the values that should result All tests that are developed can be reused whenever that device is used in other circuits Any changes to a circuits netlist will require no reworking of the test system The test developer does not need to understand the intricacies of how JTAG works

The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled Summary - Special Features n (cont. ) Enhanced Flexibilty There is no rigid order in which actions must occur n Device programming can take place before testing starts, in the middle of the testing process and at the end n n XJTAG can implement the combination of testing and programming that yields the most effective result for each circuit

The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled Summary - Special Features (cont. ) n One test system throughout the lifecycle of a circuit Designers n Test engineers n Field engineers n

XJTAG Clients The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled

The Hebrew University of Jerusalem, Israel, School of Computer-Science and Engineering, DFT and JTAG course (67703), June 2006 Ronen Peled Thank you for your attention