Jrgen at CERN Scantest DK company Electronics development

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Jørgen at CERN Scantest (DK company) Electronics development engineer 1961 1985 1986 1989 M.

Jørgen at CERN Scantest (DK company) Electronics development engineer 1961 1985 1986 1989 M. Sc. Summer Electronics Student Sonar research center, Italy CERN MIC ASIC designer 1997 PH-ED Section leader 2004 CMS pixel RD 53 Ps TDC PH-ESE Group leader TWEPP chair 2007 LHCb electronics coordinator 2012

Micro electronics at CERN 89 -04 n Design of a large variety of ASIC’s

Micro electronics at CERN 89 -04 n Design of a large variety of ASIC’s in different technologies used in many experiments world wide. n n n Fastbus slave interface chip: ALEPH , NOMAD and NA 48. Architectural/simulation study of packet switching DAQ system Time to digital converters: Drift based detectors and TOF n n n 16 channel TDC for NA 48 32 channel general purpose TDC used by multiple experiments (at CERN and outside CERN) and commercial module (CAEN) 32 channel 800 ps TDC architecture for ATLAS MDT-> Implementation at KEK Novel Pico-second resolution TDC’s and timing generators (with students) 32 channel 800 ps/200 ps/100 ps/25 ps TDC with highly flexible data driven buffering/triggering and readout architecture. n n n CMS muon detector ALICE TOF ~20 different experiments world wide Commercial modules from 3 companies 50 k chips produced HPTDC in ALICE TOF Digital architecture and first implementation of Timing and Trigger Control (TTC) ASIC for LHC experiments. n IC tester and CAE design tools. n CMOS Technologies: 1. 2 – 0, 25 um n HPTDC Gate array, Standard cell and Full custom level HPTDC in CMS muon

LHCb elec. coordination 97 - 07 n Organization and Coordination of electronics in LHCb

LHCb elec. coordination 97 - 07 n Organization and Coordination of electronics in LHCb n n n Off detector/DAQ interface module, Control interfaces, Optical links, Power supplies, front-end chips, , Radiation Review and verify electronics systems and designs: Chairing ~50 reviews n n Chaired electronics meetings in LHCb weeks Organized regular electronics workshops Indentify and enforced common solutions n n Defined, simulated and specified front-end electronics architecture. Defined interfaces to trigger, DAQ and control systems. Defined and enforced radiation hardness policy of electronics systems EMC, Equipment safety, Web pages, Power supplies, Cabling, etc. Organize electronics community in LHCb n n Architecture, Design, radiation tol. , Production, system interfaces, EMC. Define and manage general electronics infrastructure: Power distribution, racks, crates, cabling, detector safety system Services, Installation, Commissioning

PH-ESE group leader 2007 - 2011 n Merging 5 electronics groups into one global

PH-ESE group leader 2007 - 2011 n Merging 5 electronics groups into one global electronics support group servicing and driving R&D for CERN experiments. n n n Define and implement new group structure n n n Improved synergy/efficiency to handle staff retirements 65 -> 50 Support to experiments, services to HEP community, develop technologies needed for future experiments and upgrades, Coordinate HEP electronics, Organize/Participate in specific experiment projects , , Micro electronics: Rad hard technologies and HEP ASIC’s Front-end: On-detector electronics (rad hard, compact, detector interface, cooling, , ) Back-end: Off-detector electronics (DAQ , trigger, links, power, pool, ) Relocation of group into refurbished building Global project management structure and interface to experiments n Electronics steering committee n n ESE Group leader, PH management and management of experiments (Tech. + Elec. Coord. ) Electronics coordination board n n ESE Group leader and experiment representatives (Elec. Coord. ) Regular update on results/problems Central forum for global electronics issues across experiments Minimize duplication across experiments

PH-ESE n Assuring vital services to community: n n Electronics pool (~750 instruments, 5000

PH-ESE n Assuring vital services to community: n n Electronics pool (~750 instruments, 5000 movements per year) Low voltage power supplies and crates support/repair (6000 in experiments) Power distribution and racks IC technologies and associated design tools (complicated and expensive) n n n NA 62 GTK, pixel systems, strip systems, New TTC, , , Crates, Power supplies Technology transfer: Medipix/timepix/dosepix, TDC, Exchange of experience between internal experts and external groups (collaborating institutes in experiments) n n Modules Rad hard IC technologies and required design tools (130 nm + 65 nm) Rad hard optical link ( GBT ASICs and opto modules) Rad hard and magnetic field tolerant power conversion: On-detector DC/DC High density interconnect (bump bonding and TSV) Project specific R&D n n Radiation qualification, libraries, tools, MPW runs, frame contracts, export restrictions , , , Launching vital common R&D (WP) n n ICs Bi-weekly electronics seminars Well working group with a group “culture” covering all vital technologies and expertise needed. Systems, Experiments

Pixels detectors and chips 2012 n CMS phase 2 pixel electronics coordination n To

Pixels detectors and chips 2012 n CMS phase 2 pixel electronics coordination n To be installed in 2025 Unpresented challenges on pixel size (50 x 50 um 2), hit rates (3 GHz/cm 2), radiation tolerance (1 Grad , 10. 000 higher than space/mil), chip complexity (mixed signal chip with 1 billion transistors), etc. Global system: n n Definition of requirements, architecture and project organization Pixel ASIC -> RD 53 n Every 25 ns um precision Hybrid pixel Define requirements and architecture appropriate for >3 GHz/cm 2 hit rates Project/architecture definition and organization of involved groups n RD 53 collaboration: ATLAS and CMS phase 2 pixel chip n Initiated (in 2012) RD 53 collaboration to make extremely challenging next generation pixel detector ASICs for ATLAS and CMS n n n Urgent to get work started as pixel ASIC critical and looong development time Unprecedented requirements: Small pixels, 3 GHz/cm 2, 1 Grad, Readout rates, ~1 Billion transistors in 65 nm CMOS technology RD 53 demonstrator chip RD 53 co-spokesperson Formation of collaboration, LHCC proposal –> Acceptance, Collaboration framework/organization n n 4 ( plus 3) year R&D program to get to large high rate pixel ASIC RD 53 A demonstrator chip submitted last year, final chips in 2019 22 Institutes, ~150 collaborators LHCC status report: https: //indico. cern. ch/event/726320/contributions/3005309/attachments/1658484/2656006/LHCC_status_report_2018_open. pdf ATLAS Pixel Detector

Other activities n Radiation effects consultancy to the LHC n n Teaching and giving

Other activities n Radiation effects consultancy to the LHC n n Teaching and giving courses n n 64 channel 1 ps time resolution ASIC in 65 nm CMOS technology Chip submission end of next month TWEPP workshop chairman: 2014 – 2016 n n Electronics for HEP detectors (summer student lectures) Radiation effects Pico. TDC: High resolution detectors for future experiments n n Underestimated radiation effects (single event upsets very close to compromise running the LHC) Yearly workshop on electronics for high energy physics, ~200 participants CERN management liaison for Denmark n Attract more Danish students to CERN n n CERN student programs: Dedicated trainee program for Danish master/bachelor level students: And not forgetting other activities n Winter: Downhill skiing, snowboard, cross country n Summer: Mountain walking, mountain biking

Summary n CERN is a great place to work n n n Lots of

Summary n CERN is a great place to work n n n Lots of hard working and very motivated people Lots of unique technical challenges Unique international environment with people from all possible places/cultures Geneva area is a nice place to live, just next to the Jura mountains and the Alps Bringing a whole family here can be a unique opportunity with some challenges n n n Language Kids and school (extremely international environment) Work and integration of spouses

BACKUP SLIDES

BACKUP SLIDES

Background – Before CERN n 1985: Summer student at SACLANT research centre (NATO sonar

Background – Before CERN n 1985: Summer student at SACLANT research centre (NATO sonar research centre in La Spezia, Italy) n n 1986 : M. Sc. in electronics engineering n n n Development of DSP based linear sonar array calibration system based. Used to calibrate linear sonar arrays of institute. Digital signal processing Micro processor design IC design and technologies Sonar and transducers (parametric array transducer) 1986 – 1989: Electronics development engineer n n n Startup: 4 -15 employees (spin-off from larger electronics company) Commercialize IC test system developed in Danish research institute as part of EU project Develop second generation system based on ASIC’s, Bit-slice processor and FPGA’s