Java Debug Hardware Modules Using JBits by Jonathan
Java Debug Hardware Modules Using JBits by Jonathan Ballagh Eric Keller Peter Athanas Reconfigurable Architectures Workshop 2001 ®
Overview § § § § § Motivation JBits Overview Virtex Device Simulator Stimulus Hardware Modeling RAM Model Example Test Bench Design Advantages/Disadvantages Future Work/Conclusions ®
Motivation § Want to safely test RTR designs § Traditional simulators lack RTR support § Provide more flexibility than traditional simulators § “Black box” nature of the configuration bitstream A G FP § Design to bitstream translation is error prone Did we get what we wanted? ®
JBits § A Java API to configure Xilinx FPGA bitstream § Provides complete design control – Routing – CLB configuration § Supports run-time reconfiguration § Allows for tools to be built upon it § Example low-level configuration call: j. Bits. Set(row, col, S 1 F 1, S 1 F 1. SINGLE_EAST 0) ®
The JBits Environment RTP Core Library JBits API User Code JRoute API Board. Scope Debugger XHWIF TCP/IP Device Simulator ®
Virtex Device Simulator § Java based simulator for Virtex devices § Models the FPGA hardware – Interconnected flip-flops and 4 -input LUTs § Determines state information of Virtex FPGA § Allows “safe” validation of designs FPGA ®
Virtex Device Simulator § Supports simulation of RTR designs § No mechanism for generating external I/O § The problem: - How do we do test bench design? ®
Simulator Stimulus § Manage I/O in a separate process § Simulator. Client connects to Virtex. DS server § Internal FPGA states travel over TCP/IP connection Virtex. DS FPGA Internal FPGA Signals Simulator Server TCP/IP Connection Simulator Client ®
Simulator Stimulus § Signals are probed and stimulated through JBits Pin resources § Example JBits Pin declaration: Row Column Pin reg_pin = new Pin(pin. CLB, 4, 9, Center. Wires. S 0_XQ); CLB, IOB, BRAM, or DLL JBits Resource ®
Simulator Stimulus - Functions § Pins are read using read. Pin. Value (Pin) § Vectors are read using read. Vector(Pin[] IOPins) § Pins are written using set. Pin. Value(Pin, int) § Vectors are written using write. Vector(int val, Pin[] IOPins) § Method wait. For. Step() waits for simulator clock to be stepped ®
Hardware Modeling § Models extend Simulator. Client class § Devices are modeled using behavioral Java code § Examples: Memory Processor Control Signal Manipulation § Limited only by the resources available to the “host” machine ®
Model Operation § Generic model operation: Initialization Read Pin Values from Simulator Determine Next State File I/O Write Pin Values to Simulator Wait for Clock Step ®
Example: RAM public class RAMClient extends Simulator. Client /* class member fields */ private int[] RAMContents; private Pin[] addr. Pins; private Pin[] data. Pins; private Pin RWPin; private Pin CEPin; /** * Creates * * @param * @param * */ /* /* /* { array storing memory values */ RAM address pins */ RAM data I/O pins */ RAM read/write pin */ RAM chip enable pin */ an instance of the RAMClient _addr. Pins - collection of RAM addr pins _data. Pins - collection of RAM data pins _RWPin - RAM read/write pin _CEPin - RAM chip enable pin _RAMContents - RAM memory values public RAMClient(Pin[] _addr. Pins, Pin[] _data. Pins, Pin _RWPin, Pin _CEPin, int[] _RAMContents) {. . . ®
Example: RAM while (step. Count < max. Steps) { /* obtain RAM address */ address = read. Vector(addr. Pins); /* check CEPin status */ if (read. Value(CEPin) == 0) { /* active low */ /* check the r/w status */ if (read. Value(RWPin) == 0) /* write */ RAMContents[address] = read. Vector(data. Pins); else /* read */ write. Vector(RAMContents[address], data. Pins); } /* end if */ /* wait for Virtex. DS to be stepped */ wait. For. Step(); step. Count++; } /* end while */ ®
Test Bench Design Virtex. DS Models FP …. …. …. . GA XHWIF Vector Files …. …. …. . GUI(s) Board. Scope ®
Advantages § Java language easily models design § Allows hardware level simulation involving proto type hardware components § Supports RTR, unlike traditional VHDL simulators § Testbench can be designed for any Virtex bitstream – Design tool is irrelevant ®
Disadvantages § Only supports Virtex devices § No way to view asynchronous events § Only one device simulator can be open at a time § Very “low-level”… ®
Future Work § Only 1 Virtex. DS can be open at a time § Allow direct access to Virtex. DS event queues, rather than with a TCP/IP connection. § Allow primitives to generate events on external models. This would allow for better timing models. § Communication between external modules § Add asynchronous event support § Use JBits User Constraints File Parser to automatically obtain Pin locations ®
Conclusions § Provides a method to model external hardware § Allows bitstream level debugging with Virtex. DS – Which means that it supports RTR § More flexible than VHDL testbenches § Graphical model representations can be designed to complement the Board. Scope graphical debugger. ®
Questions? ®
- Slides: 20