ISPD 2005 ISPD 2005 A New Era for

ISPD 2005 ISPD - 2005 A New Era for CAD Gary Smith Chief Analyst Design & Engineering

The Automation of RTL Design 2005 n The IC Implementation Tool Set automated RTL input to GDS II n The RTL Functional Verification Tool Suite automated RTL input to GDS II n But GDS II is no longer sufficient.

The Automation of the RTL Methodology (from DQ@DAC 2005) Moved to the R T L ES Level V e r i f i c a t i o n Intelligent Test Bench RTL Simulation Formal Verification Formal Analysis Acceleration and Emulation RTL Design Tools GDS II Sign-Off Silicon Virtual Prototype Physical Synthesis DFT Timing, Signal-Integrity and Power Analysis IC Place and Route GDS II ? RTL Sign-Off I C Just becoming I m p l e m e n t a t i o n Reality

The IC Implementation Toolset (from DQ@DAC 2002) n This is the RTL to GDS II tool flow n The functions within the toolset (as a minimum) include logic synthesis; timing, signal-integrity and power analysis; probably DFT and clock tree synthesis; IC place and route (final route is being questioned by some ASIC vendors) n The market has been all but wrapped up by Synopsys, Magma and Cadence

What Happened ? Tool Set IC Implementation ESL GDS II DFM Correction & IC “re”-Layout Mask Shop

But it Didn’t Yield !!! n The COT Crisis at 130 nm. - The August 2001 awakening. n Who’s Responsible !!! - The Designer - The Foundry - The Mask Shop will fix it ! n But will they ?

The Era of Disaggregation n The 1990 s were the Cream Puff era of Semiconductors. n Plain old vanilla CMOS was king. n Other processes, such as Silicon on Insulator and Ga. As, were only niche players. n Process improvements were all incremental. n The Foundry model grew rapidly. n The RTL Methodology drove design the entire decade. n It was all so easy.

Back to the Future ! n This Decade is looking more like the 1980 s. n Process R&D and Device Physics are a vital part of an IDM’s competitive profile. n Will the Foundries be laggards ? n Is this the end of CMOS, at least plain old vanilla CMOS ? n What does the new transistor look like at 45 nm ? n Engineers are moving up to the ES Level of design.

Competitive Re-aggregation n IDMs and Foundries are moving the Mask Shop back In-House. n ASIC Vendors are doing a majority of the IC Layout In. House again. n Twenty Seven Percent of the designers are using some In-House developed tools. n Mainstream OEMs are looking for ASIC vendors to take an RTL design Hand-off. n Is COT a shrinking business model ? n Will the IDMs/Foundries buy up the DFM vendors to keep their new process information proprietary ?

The Migration of Design Engineers So. C Design Opportunities are Driven by Applications ESL RTL CAD So. C Implementation Challenges are Driven by Silicon

Today’s Challenges and Opportunities ESL CAE RTL CAD DFM

The IC Layout Team comes to the Rescue n The Mask Shops are facing shrinking business and shrinking margins. n The Design Team just learned circuit design; they aren’t ready for Layout issues. n The IC Layout team was supposed to go away with the new IC Implementation Tool Sets. n Now they are the second fastest growing EE segment.

The Migration of DFM Technology n There are three DFM markets. - The Fab engineer - The IC Layout Engineer - The Design Engineer n Tools for the FAB engineer will be a specific market, but fairly small. - And no they won’t pay royalties. n The IC Layout Engineer will be the main market. n The Design Engineer will use tools that incorporate the last generation of DFM tools and methods.

A New Era for CAD n So CAD won’t go away “as expected”. n “If” the EDA industry provides the tools “on time” it will continue to be a growing market. n “If not” the tools will increasingly be built In-House by the Semiconductor vendors. n There is no reason to expect that the CAD market won’t continue to supply tools once we enter the nonsilicon era of Semiconductors.