ISAs and Microarchitectures Instruction Set Architecture The interface

ISAs and Microarchitectures • Instruction Set Architecture • • • The interface between hardware and software “Language” + programmer visible state + I/O = ISA Hardware can change underneath Software can change above Example: IA 32, IA 64, ALPHA, POWERPC • Microarchitecture • An implementation of an ISA – Pentium Pro, 21064, G 5, Xeon • Can tune your code for specific microarchitecures • Machine architecture • Processor, memory, buses, disks, nics, …. • Can also tune code for this – 1–

ISAs Continued • State • Memory in all its forms – Registers • I/O • Special memory locations that are read/written by other devices • Processor reading/writing them causes side-effects in the devices • Interrupts • Language • How to interpret bits as transformations from State+I/O into State+I/O – How to tell the “cone of logic” what to do – 2–

Different models • CISC = Complex Instruction Set Computer • • RISC = Reduced Instruction Set Computer • • Push machine language closer to the hardware Hope: easier for compiler to produce high performance Alpha, Power. PC, … Others • • • Push machine language closer to programming languages Hope: more abstraction => more performance IA 32, VAX, IBM mainframe processors, … (V)LIW = (Very) Long Instruction Word : IA 64 Vector processors: Cray, Hitachi, Altivec, SSV, … Multithreaded: Tera Reconfigurable (you write the cone of logic directly) Transistors are first order effect in market – 3–

Stack Machines Instructions stored in memory sequentially (Same as the IA 32 as we’ll see) Instead of registers, only a stack instruction operate on the stack 10 + 20 – 30 => 10 20 + 30 push 10 push 20 add push 30 sub – 4–

Stack Machines Modern machines are not stack machines - parallelism hard due to contention at top of stack Modern language virtual machines are Java Virtual Machine Microsoft Common Language Run-time Idea: compiler generates code for the abstract virtual stack machine. Virtual machine is native software that interprets that stack machine code Why: Portability: implement compiler once, implement virtual machine (small) for each architecture – 5–

Stack Machines But what about performance? Just In Time compilers (JITs) Idea: virtual machine notices which code it spends the most time executing and---at run time---compiles it from code for the stack machine to code for the physical machine. Your program executes as a combination of interpretted stack machine code and native code (the “hot spots”) Why does this work? Locality! Code that contributes in a large way to run time is almost always repeated (iteration, recursion, …) – 6–

IA 32 Processors Totally Dominate Computer Market Evolutionary Design • First microprocessor: 4004 (1971, 4 bit, 2300 transistors) • Starting in mid ’ 70 s with 8080 (1974, 8 bit, 6000 transistors) • 1978 – 16 bit 8086 (1978, 16 bit, 29000 transistors) – 8088 version used in IBM PC – 1981 – Growth of PC • Added more features as time goes on • Still support old features, although obsolete Complex Instruction Set Computer (CISC) • Many different instructions with many different formats – But, only small subset encountered with Linux programs • Hard to match performance of Reduced Instruction Set Computers (RISC) • But, Intel has done just that! – 7–

X 86 Evolution: Programmer’s View Name 8086 1978 Date 29 K Transistors • 16 -bit processor. Basis for IBM PC & DOS • Limited to 1 MB address space. DOS only gives you 640 K 80286 1982 134 K • Added elaborate, but not very useful, addressing scheme • Basis for IBM PC-AT, 16 bit OS/2, and 16 -bit Windows 386 1985 275 K • Extended to 32 bits. Added “flat addressing” • Capable of running Unix, 32 bit Windows, 32 bit OS/2, … • Linux/gcc uses no instructions introduced in later models 486 1989 1. 9 M Pentium 1993 Pentium Pro 1995 3. 1 M 5. 5 M big change in microarchitecture Future chips used microarchitecture for years. – 8–

X 86 Evolution: Programmer’s View Name Date Pentium/MMX Transistors 1997 4. 5 M • Added special collection of instructions for operating on 64 -bit vectors of 1, 2, or 4 byte integer data Pentium II 1997 7 M • Added conditional move instructions Pentium III 1999 8. 2 M • Added “streaming SIMD” instructions for operating on 128 -bit vectors of 1, 2, or 4 byte integer or floating point data Pentium 4 2001 42 M • Added 8 -byte formats and 144 new instructions for streaming SIMD mode • Big change in underlying microarchitecture Xeon HT 2003 100 M • Multiple cores (“hyperthreading”), larger caches AMD Opteron 2003 100 M • 64 bit extensions, large caches Xeon ? 2005+? 150 M • Virtual machine extensions, 64 bit extensions, multiple cores, larger caches – 9–

Why so many transistors ISA of P 4 is basically the same as 386, but it uses 150 times more transistors Answer: Hardware extracts parallelism out of code stream to get higher performance multiple issue pipelining out-of-order and speculative execution All processors do this these days Limits to how far this can go, hence newer ISA ideas – 10 –

New Species: IA 64 Name Date Transistors Itanium 2000 10 M • Extends to IA 64, a 64 -bit architecture • Radically new instruction set designed for high performance • Will be able to run existing IA 32 programs – On-board “x 86 engine” • Has proven to be problematic. The principles of machine-level programming we will discuss will apply to current processors, CISC and RISC. Some principles will also apply to LIWs like IA 64 Quantum Computers, if we can build them and if they are actually more powerful than classical computers, will be COMPLETELY DIFFERENT – 11 –

ISA / Machine Model of IA 32 CPU Memory Addresses E I P Registers Data Condition Codes Instructions Stack Programmer-Visible State • EIPProgram Counter – Address of next instruction • Register File – Heavily used program data • Condition Codes – Store status information about most recent arithmetic operation – Used for conditional branching Object Code Program Data OS Data • Memory – Byte addressable array – Code, user data, (some) OS data – Includes stack used to support procedures – 12 –

Turning C into Object Code • Code in files p 1. c p 2. c • Compile with command: gcc -O p 1. c p 2. c -o p – Use optimizations (-O) (versus –g => debugging info) – Put resulting binary in file p text C program (p 1. c p 2. c) Compiler (gcc -S) text Asm program (p 1. s p 2. s) Assembler (gcc or as) binary Object program (p 1. o p 2. o) Linker (gcc or ld) binary Executable program (p) – 13 – Static libraries (. a)

Compiling Into Assembly C Code int sum(int x, int y) { int t = x+y; return t; } Generated Assembly _sum: pushl %ebp movl %esp, %ebp movl 12(%ebp), %eax addl 8(%ebp), %eax movl %ebp, %esp popl %ebp ret Obtain with command gcc -O -S code. c Produces file code. s – 14 –

Assembly Characteristics Minimal Data Types • “Integer” data of 1, 2, or 4 bytes – Data values – Addresses (untyped pointers) • Floating point data of 4, 8, or 10 bytes • No aggregate types such as arrays or structures – Just contiguously allocated bytes in memory Primitive Operations • Perform arithmetic function on register or memory data • Transfer data between memory and register Data Flow – Load data from memory into register – Store register data into memory • Transfer control – Unconditional jumps to/from procedures Control Flow – Conditional branches – 15 –

Object Code for sum 0 x 401040 <sum>: 0 x 55 • Total of 13 0 x 89 bytes 0 xe 5 • Each instruction 0 x 8 b 1, 2, or 3 bytes 0 x 45 • Starts at 0 x 0 c address 0 x 03 0 x 401040 0 x 45 0 x 08 0 x 89 0 xec 0 x 5 d 0 xc 3 Assembler • Translates. s into. o • Binary encoding of each instruction • Nearly-complete image of executable code • Missing linkages between code in different files Linker • Resolves references between files • Combines with static run-time libraries – E. g. , code for malloc, printf • Some libraries are dynamically linked – Linking occurs when program begins execution – 16 –

Machine Instruction Example C Code • Add two signed integers int t = x+y; Assembly addl 8(%ebp), %eax Similar to expression x += y 0 x 401046: 03 45 08 • Add 2 4 -byte integers – “Long” words in GCC parlance – Same instruction whether signed or unsigned • Operands: x: Register %eax y: Memory M[%ebp+8] t: Register %eax » Return function value in %eax Object Code • 3 -byte instruction • Stored at address 0 x 401046 – 17 –

Disassembling Object Code Disassembled 00401040 <_sum>: 0: 55 1: 89 e 5 3: 8 b 45 0 c 6: 03 45 08 9: 89 ec b: 5 d c: c 3 d: 8 d 76 00 push mov add mov pop ret lea %ebp %esp, %ebp 0 xc(%ebp), %eax 0 x 8(%ebp), %eax %ebp, %esp %ebp 0 x 0(%esi), %esi Disassembler objdump -d p • • Useful tool for examining object code Analyzes bit pattern of series of instructions Produces approximate rendition of assembly code Can be run on either a. out (complete executable) or. o file – 18 –

Alternate Disassembly Disassembled Object 0 x 401040: 0 x 55 0 x 89 0 xe 5 0 x 8 b 0 x 45 0 x 0 c 0 x 03 0 x 45 0 x 08 0 x 89 0 xec 0 x 5 d 0 xc 3 0 x 401040 0 x 401041 0 x 401043 0 x 401046 0 x 401049 0 x 40104 b 0 x 40104 c 0 x 40104 d <sum>: <sum+1>: <sum+3>: <sum+6>: <sum+9>: <sum+11>: <sum+12>: <sum+13>: push mov add mov pop ret lea %ebp %esp, %ebp 0 xc(%ebp), %eax 0 x 8(%ebp), %eax %ebp, %esp %ebp 0 x 0(%esi), %esi Within gdb Debugger gdb p disassemble sum • Disassemble procedure x/13 b sum • Examine the 13 bytes starting at sum – 19 –

What Can be Disassembled? % objdump -d WINWORD. EXE: file format pei-i 386 No symbols in "WINWORD. EXE". Disassembly of section. text: 30001000 <. text>: 30001000: 55 30001001: 8 b ec 30001003: 6 a ff 30001005: 68 90 10 00 30 3000100 a: 68 91 dc 4 c 30 push mov push %ebp %esp, %ebp $0 xffff $0 x 30001090 $0 x 304 cdc 91 • Anything that can be interpreted as executable code • Disassembler examines bytes and reconstructs assembly source – 20 –

Copying Data and Registers Moving Data (Really Copying) movl Source, Dest: Move 4 -byte (“long”) word • Accounts for 31% of all instructions in sample (IA 32 – other machines are different) Operand Types • Immediate: Constant integer data – Like C constant, but prefixed with ‘$’ – E. g. , $0 x 400, $-533 – Encoded with 1, 2, or 4 bytes • Register: One of 8 integer registers – But %esp and %ebp reserved for special use – Others have special uses for particular instructions – Special cases => Non-orthogonality (BAD) • Memory: 4 consecutive bytes of memory – Various “addressing modes” – 21 – %eax %edx %ecx %ebx %esi %edi %esp %ebp

movl Operand Combinations Source movl Destination C Analog movl $0 x 4, %eax temp = 0 x 4; movl $-147, (%eax) *p = -147; Imm Reg Mem movl %eax, %edx temp 2 = temp 1; movl %eax, (%edx) *p = temp; Mem Reg movl (%eax), %edx temp = *p; • Cannot do memory-memory transfers with single instruction – Example of NON-ORTHOGONALITY in the IA 32 ISA » Makes it much harder to program or compile for – 22 –

Simple Addressing Modes Normal (R) Mem[Reg[R]] • Register R specifies memory address movl (%ecx), %eax => int t = *p; Displacement D(R) Mem[Reg[R]+D] • Register R specifies start of memory region • Constant displacement D specifies offset movl 8(%ecx), %edx => int t = p[2]; movl 8(%ebp), %edx => int t = some_argument; – %ebp, %esp used to reference stack. Stack contains arguments to function All instructions support addressing modes, not just moves – 23 –

Using Simple Addressing Modes void swap(int *xp, int *yp) { int t 0 = *xp; int t 1 = *yp; *xp = t 1; *yp = t 0; } swap: pushl %ebp movl %esp, %ebp pushl %ebx movl movl 12(%ebp), %ecx 8(%ebp), %edx (%ecx), %eax (%edx), %ebx %eax, (%edx) %ebx, (%ecx) movl -4(%ebp), %ebx movl %ebp, %esp popl %ebp ret – 24 – Set Up Body Finish

Understanding Swap void swap(int *xp, int *yp) { int t 0 = *xp; int t 1 = *yp; *xp = t 1; *yp = t 0; } • • • Offset Stack 12 yp 8 xp 4 Rtn adr 0 Old %ebp Register %ecx %edx %eax %ebx Variable yp xp t 1 t 0 %ebp -4 Old %ebx movl movl 12(%ebp), %ecx 8(%ebp), %edx (%ecx), %eax (%edx), %ebx %eax, (%edx) %ebx, (%ecx) – 25 – # # # ecx edx eax ebx *xp *yp = = = yp xp *yp (t 1) *xp (t 0) eax ebx

Indexed Addressing Modes Most General Form D(Rb, Ri, S) Mem[Reg[Rb]+S*Reg[Ri]+ D] • D: Constant “displacement” 1, 2, or 4 bytes • Rb: Base register: Any of 8 integer registers • Ri: Index register: Any, except for %esp All instructions – Unlikely you’d use %ebp, either support • S: Scale: 1, 2, 4, or 8 Special Cases (Rb, Ri) D(Rb, Ri) (Rb, Ri, S) addressing modes, not just moves Mem[Reg[Rb]+Reg[Ri]] Mem[Reg[Rb]+Reg[Ri]+D] Mem[Reg[Rb]+S*Reg[Ri]] – 26 –

Address Computation Instruction leal Src, Dest • Src is address mode expression • Set Dest to address denoted by expression Uses • Computing address without doing memory reference – E. g. , translation of p = &x[i]; • Computing arithmetic expressions of the form x + k*y – k = 1, 2, 4, or 8. – 27 –

Some Arithmetic Operations Format Computation Two Operand Instructions addl Src, Dest subl Src, Dest imull Src, Dest sarl Src, Dest shrl Src, Dest xorl Src, Dest andl Src, Dest orl Src, Dest Dest Dest = = = = = Dest Dest Dest + Src - Src * Src << Src >> Src ^ Src & Src | Src One Operand Instructions incl Dest decl Dest negl Dest notl Dest Dest = = Dest + 1 Dest - 1 - Dest ~ Dest – 28 – Also called shll Arithmetic Logical

Using leal for Arithmetic Expressions int arith (int x, int y, int z) { int t 1 = x+y; int t 2 = z+t 1; int t 3 = x+4; int t 4 = y * 48; int t 5 = t 3 + t 4; int rval = t 2 * t 5; return rval; } arith: pushl %ebp movl %esp, %ebp movl 8(%ebp), %eax movl 12(%ebp), %edx leal (%edx, %eax), %ecx leal (%edx, 2), %edx sall $4, %edx addl 16(%ebp), %ecx leal 4(%edx, %eax), %eax imull %ecx, %eax movl %ebp, %esp popl %ebp ret – 29 – Set Up Body Finish

Understanding arith int arith (int x, int y, int z) { int t 1 = x+y; int t 2 = z+t 1; int t 3 = x+4; int t 4 = y * 48; int t 5 = t 3 + t 4; int rval = t 2 * t 5; return rval; } movl 8(%ebp), %eax movl 12(%ebp), %edx leal (%edx, %eax), %ecx leal (%edx, 2), %edx sall $4, %edx addl 16(%ebp), %ecx leal 4(%edx, %eax), %eax imull %ecx, %eax # # # # Offset • • • 16 z 12 y 8 x 4 Rtn adr 0 Old %ebp eax edx ecx eax – 30 – = = = = x y x+y (t 1) 3*y 48*y (t 4) z+t 1 (t 2) 4+t 4+x (t 5) t 5*t 2 (rval) Stack %ebp

Another Example int logical(int x, int y) { int t 1 = x^y; int t 2 = t 1 >> 17; int mask = (1<<13) - 7; int rval = t 2 & mask; return rval; } logical: pushl %ebp movl %esp, %ebp movl xorl sarl andl movl %ebp, %esp popl %ebp ret 213 = 8192, 213 – 7 = 8185 movl xorl sarl andl 8(%ebp), %eax 12(%ebp), %eax $17, %eax $8185, %eax eax eax = = – 31 – x x^y (t 1) t 1>>17 (t 2) t 2 & 8185 Set Up Body Finish

CISC Properties Instruction can reference different operand types • Immediate, register, memory Arithmetic operations can read/write memory Memory reference can involve complex computation • Rb + S*Ri + D • Useful for arithmetic expressions, too Instructions can have varying lengths • IA 32 instructions can range from 1 to 15 bytes RISC • Instructions are fixed length (usually a word) • special load/store instructions for memory – Generally simpler addressing modes • Other operations use only registers (but there are lots of registers) – 32 –

Summary: Abstract Machines Machine Models C mem proc Assembly mem Stack regs alu Cond. processor Codes Data 1) char 2) int, float 3) double 4) struct, array 5) pointer Control 1) loops 2) conditionals 3) goto 4) Proc. call 5) Proc. return 1) byte 3) branch/jump 2) 4 -byte long word 4) call 3) 8 -byte quad word 5) ret 4) contiguous byte allocation 5) address of initial byte – 33 –

History Pentium Pro (P 6) • Announced in Feb. ‘ 95 • Basis for Pentium II, Pentium III, and Celeron processors Features • Dynamically translates instructions to more regular format – Very wide, but simple instructions • Executes operations in parallel – Up to 5 at once • Very deep pipeline – 12– 18 cycle latency – 34 –

Pentium. Pro Block Diagram Microprocessor Report 2/16/95

Pentium. Pro Operation Translates instructions dynamically into “Uops” • 118 bits wide • Holds operation, two sources, and destination Executes Uops with “Out of Order” engine • Uop executed when – Operands available – Functional unit available • Execution controlled by “Reservation Stations” – Keeps track of data dependencies between uops – Allocates resources Consequences • Indirect relationship between IA 32 code & what actually gets executed • Difficult to predict / optimize performance at assembly level – 36 –

Whose Assembler? Intel/Microsoft Format GAS/Gnu Format lea sub cmp mov leal subl cmpl movl eax, [ecx+ecx*2] esp, 8 dword ptr [ebp-8], 0 eax, dword ptr [eax*4+100 h] (%ecx, 2), %eax $8, %esp $0, -8(%ebp) $0 x 100(, %eax, 4), %eax Intel/Microsoft Differs from GAS • Operands listed in opposite order mov Dest, Src movl Src, Dest • Constants not preceded by ‘$’, Denote hexadecimal with ‘h’ at end 100 h $0 x 100 • Operand size indicated by operands rather than operator suffix subl • Addressing format shows effective address computation [eax*4+100 h] $0 x 100(, %eax, 4) – 37 –