Is Overlay Error More Important Than Interconnect Variations

Outline • Traditional BEOL Variation and Process • Double Patterning Lithography (DPL) • Overlay

Traditional BEOL Variation and Process • Sources of variation: • Metal/dielectric densitydependent, systematic •

Double Patterning Lithography • Double Patterning Lithography (DPL) • Pattern-doubling: ‘ 2 X-resolution’ lithography

Double Patterning Lithography Options • Double Exposure • Double Patterning • Spacer-DP Target layer

Introduction to the Variability in DPL • Overlay error • Alignment metric • Causes:

Overlay Error in Various DPL Options • Impact on interconnect parameter in DPL options

Mask Coloring and Layout Examples in DPL • Mechanism of misalignment-induced variation 2 4

TCAD-Based Analysis Setup • Test structure M+1 layer S M layer D W H

TCAD-Based Analysis Results • Overlay vs. width vs. height Capacitance (a. F/um) • Indirect

Design-Level Analysis Flow • Overlay-aware extraction flow 1. Design GDS 2. Split GDS Non-DPL

Design-Level Analysis DOE • Design of Experiments for DE/DP with DA 1. foreach layer

Impact on Capacitance Variation • Total interconnect capacitance: maximum C(%) • Among top 20%

Impact on Crosstalk-Induced Delay • Maximum coupling induced delay change • Prime. Time-SI (Synopsys)

Impact on Timing • Longest path and total negative slack (TNS) • Impact of

Conclusions • We provide a variational interconnect analysis technique for double patterning lithography •

BACKUP UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009

Misalignment Under M 1 Layer (Standard-Cell) • Standard cell structure Original • Assumptions P

Experimental Results on Standard Cell RED: Original. Blue: Shift one set of gates Green:

DPL Options • Double Exposure • Double Patterning Resist Hardmask Target layer Resist Target

Impact of Overlay in Positive DE/DP mask 1 mask 2 (misaligned to left) Positive

Impact of Overlay in Negative DE/DP mask 1 mask 2 (misaligned to left) Negative

Impact of Overlay in Positive SDP Primary patterns Spacers (act as if masks) (kind

Electrical Impacts: Capacitance Variation 15 10 5 0 -5 -10 Max increase Mean Max

M 2 |S|/2 M 4 |S| P-DE/DP |S|/2 N-DE/DP |S|/2 P-SDP |S|/2 N-SDP UCSD

Maximum Crosstalk Induced Delay • A net has maximum crosstalk-induced delay Crosstalk Delay Variation

Total Negative Slack Variation Normalized TNS (%) • SDP, especially for lower layer (smaller

Slides: 34

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Is Overlay Error More Important Than Interconnect Variations in Double Patterning Kwangok Jeong: ECE Dept. , UC San Diego Andrew B. Kahng: ECE and CSE Dept. , UC San Diego Rasit O. Topaloglu: GLOBALFOUNDRIES, Inc. UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 1

Outline • Traditional BEOL Variation and Process • Double Patterning Lithography (DPL) • Overlay Error in Double Patterning • TCAD-Based Analysis • Design-Level Analysis • Conclusions UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 2

Traditional BEOL Variation and Process • Sources of variation: • Metal/dielectric densitydependent, systematic • Random process variation • Results of variation • Width (W) variation • Metal height (H) variation • Dielectric thickness (D) variation • Traditional backend of the line (BEOL) Process MATERIALS: Resist Dielectric STEPS: coating Mask exposure M+1 etch W H M D M-1 Copper Cu filling UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 4

Double Patterning Lithography • Double Patterning Lithography (DPL) • Pattern-doubling: ‘ 2 X-resolution’ lithography with traditional ‘ 1 X-resolution’ equipment Resist Dielectric Mask 1 1 X 1 st Exposure Mask 2 1 X 2 nd Exposure 1 X-resolution 2 X-resolution • Options for double patterning lithography • Process: Double Exposure (DE) / Double Patterning (DP) / Spacer Double Patterning (SDP) • Resist-type: Positive-tone / Negative tone • Target Feature: Line / Spacing UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 6

Double Patterning Lithography Options • Double Exposure • Double Patterning • Spacer-DP Target layer Litho-etch 2 nd Litho-etch mask hardmask • Photoresist Litho-etch & Spacer Formation 1 st positive resist negative resist Cu Dielectric Etch Poly Spacer • Target Feature (a) Spaces (b) Lines (a) Positive-tone (b) Negative-tone UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 7

Introduction to the Variability in DPL • Overlay error • Alignment metric • Causes: Mask 1 • mask misalignment, • material stress-impacted Mask 2 deformations, S • litho/etch-impacted Reference S topography, Indirect • lens aberration, etc. alignment • Results in: • Width variation • Space (or pitch) variation C c C g Capacitance variation S S Direct alignment • Indirect: • Two DPL masks aligned to a reference layer • Error: • Direct: • Second DPL mask aligned to the first DPL mask • Error: UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 9

Overlay Error in Various DPL Options • Impact on interconnect parameter in DPL options • P (pitch), W (width), W’ W W”, P’ P P’’ S 1 S 2 1 W W P’ 2 1 1 2 1 W’’ W’ P’’ P Positive DE/DP SPACE 2 P 1 S/2 Negative DE/DP WIDTH S S 1 S S 2 1 W’’ W P 2 1 P Positive SDP WIDTH & SPACE 1 2 1 W’ W’ P’’ 2 1 P’ Negative SDP WIDTH & SPACE UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 10

Mask Coloring and Layout Examples in DPL • Mechanism of misalignment-induced variation 2 4 6 1 Coloring 6 3 5 Original patterns 1 S 6 Patterns 1 3 Patterns 2 (a) DE and DP Process Dummy for pattern 6 2 4 S 2 5 3 5 Original patterns 1 6 1 3 5 4 Spacer (gray) Narrow space a b W 1 35 6 Coloring Spacer formation (Large spacer) Trim & repair (dark gray) W” (b) SDP Process UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 11

TCAD-Based Analysis Setup • Test structure M+1 layer S M layer D W H M-1 layer • Design of experiments (DOE) • Full combinations of W, H, D and S • For all DE/DP/SDP with positive/negative-tone resist • 3 variation: We assume 20% of nominal value D: dielectric height W: line width H: line height S: overlay shift 1. for (i = -3 ; i 3 ; i=i+1) { 2. for (j = -3 ; j 3 ; j=j+1) { 3. for (k = -3 ; k 3 ; k=k+1) { 4. for (l = -3 ; l 3 ; l=l+1) { 5. W=Wnom + i W 3 6. H= Hnom + j H 3 7. D= Dnom + k D 3 8. S = Snom + l S 3 9. run field solver over parameterized structure}}} 8. Find nominal and worst-case capacitance UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 13

TCAD-Based Analysis Results • Overlay vs. width vs. height Capacitance (a. F/um) • Indirect alignment shown: • • Impact of overlay: 0 ~ 2. 4% of C-total Impact of width: -13% ~ 10% of C-total Impact of height: -32% ~ 18% of C-total Impact of indirect alignment ~ 2 x direct alignment UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 14

Outline • Traditional BEOL Variation and Process • Double Patterning Lithography (DPL) • Overlay Error in Double Patterning • TCAD-Based Analysis • Design-Level Analysis • Conclusion UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 15

Design-Level Analysis Flow • Overlay-aware extraction flow 1. Design GDS 2. Split GDS Non-DPL layers Base GDS Sub-GDS 1 Sub-GDS 2 AES core with Nan. Gate 45 nm Tech. ILP-based min cost coloring (Kahng et al. ICCAD 08) TOP. GDS Initial GDS 3. Pattern Decomposition Sub-GDS 1 -1 Coloring and Splitting Sub-GDS 1 -2 Sub-GDS 2 -1 4. Shift and Merge (Cadence Virtuoso) Sub-GDS 2 -2 5. Resize and Extraction (Synopsys Hercules, Star-RCXT) Shifting and Merging TOP. GDS Resizing UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 16

Design-Level Analysis DOE • Design of Experiments for DE/DP with DA 1. foreach layer { M 2, M 3, M 4, M 5 } 2. decompose layer into layermask 1 and layermask 2 3. foreach S { -3 /2, -2 /2, - /2, 0, /2, 2 /2, 3 /2} 4. shift layermask 1 by S 5. shift layermask 2 by –S 6. end 7. layermask 1 + layermask 2 8. foreach W { -3 /2, -2 /2, - /2, 0, /2, 2 /2, 3 /2} 9. resize layer by W 10. end 11. merge with other layers 12. RC-Extraction and Timing Analysis 13. end UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 17

Impact on Capacitance Variation • Total interconnect capacitance: maximum C(%) • Among top 20% high capacitance nets • Impact of overlay < impact of width Overlay Width Min -7. 7% -22. 2% -3 Avg 1. 4% 4. 7% Max 9. 2% 7. 1% Min -7. 3% -3. 6% +3 Avg 1. 4% 5. 3% Max 9. 7% 28. 6% • Sum of capacitance in the most critical path • Critical path has short interconnects impact of BEOL variation significantly reduces • Impact of overlay < impact of width Overlay Width Interconnect only Min Max -0. 08% 0. 47% -1. 87% 2. 59% Interconnect + Gate Min Max -0. 04% 0. 25% -0. 99% 1. 38% UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 18

Impact on Crosstalk-Induced Delay • Maximum coupling induced delay change • Prime. Time-SI (Synopsys) is used to find a net that is mostly affected due to crosstalk • Temporal/functional filtering is performed • Selected net structure M 2 segment: 1. 604 um M 3 segment: 0. 78 um M 4 segment: 14. 788 um • A net with relatively small length (~17 um) can have >10% delay changes due to overlay error Overlay Width Cc (p. F) Cg (p. F) @Min @Max 1. 842 1. 863 1. 089 1. 053 1. 840 1. 906 1. 089 1. 120 Delay Min Max -0. 47% 13. 1% -0. 82% 15. 4% Capacitance when Delay is maximum Capacitance when Delay is minimum UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 19

Impact on Timing • Longest path and total negative slack (TNS) • Impact of overlay << impact of width • Longest path delay changes negligibly • However, overall timing (TNS) can change significantly Longest path delay Min Max -0. 06% 0. 98% -1. 22% 2. 00% Total Negative Slack (ns) Overlay Width TNS Min 3. 2% -34. 3% Max 3. 8% 49. 4% -60 -50 -40 -30 -20 Overlay Width -10 0 -3 s -2 s -1 s 0 s 1 s 2 s 3 s Interconnect variation UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 20

Conclusions • We provide a variational interconnect analysis technique for double patterning lithography • We analyze interconnect variations due to overlay error in DPL • We augment previous work by providing both interconnect and chip-level RCextraction framework reflecting interconnect variation in a 45 nm DPL process • We compare the impact of overlay error with traditional interconnect variations • Summary of observations • Indirect alignment results in higher variation than direct alignment • In most analysis, impact of traditional variation source ( width) is larger than that of overlay error, however, overlay error is additive and non-negligible • Overlay error can cause up to 10% capacitance variation and 13% increase of crosstalk-induced delay • Ongoing/Future Work • Impact in the presence of metal fills • More in-depth analysis or remaining DPL process options • Process sensitivity analysis UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 22

BACKUP UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 23

Misalignment Under M 1 Layer (Standard-Cell) • Standard cell structure Original • Assumptions P 1 P 2 (a) M C BASE (b) • There exist a reference coordinate to measure misalignment • 10 nm misalignment is a maximum displaced distance from the reference coordinate • Possible moves • • Poly 1: left 10 nm (L) / 0 nm (C) /right 10 nm (R) Poly 2: left 10 nm (L) / 0 nm (C) /right 10 nm (R) M 1: left 10 nm (L) / 0 nm (C) /right 10 nm (R) Contact: left 10 nm (L) / 0 nm (C) /right 10 nm (R) • All Combinations = 3*3*3*3 = 81 cases • Naming convention for each testcase • P 1{direction}_P 2{direction}_C{direction}_M{direction} • E. g. , “P 1 C_P 2 L_CC_MC” means even gates move lef t by 10 nm UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 24

Experimental Results on Standard Cell RED: Original. Blue: Shift one set of gates Green: Shift M 1 and Cont. (same direction) Poly 1 (-10 nm) Rise Delay (S) Poly 2 (-10 nm) Poly 2 (+10 nm) Poly 1 (0 nm) M 1 (-10 nm) Contact (-10 nm) (+10 nm) (-10 nm) 1. 302 E-10 1. 307 E-10 Contact (0 nm) 1. 307 E-10 Contact (+10 nm) 1. 307 E-10 Contact (-10 nm) 1. 338 E-10 Contact (+10 nm) 1. 338 E-10 M 1 (0 nm) 1. 298 E-10 1. 303 E-10 1. 335 E-10 M 1 (+10 nm) 1. 299 E-10 1. 304 E-10 1. 335 E-10 M 1 (-10 nm) 1. 286 E-10 1. 291 E-10 1. 290 E-10 1. 291 E-10 1. 296 E-10 1. 295 E-10 M 1 (0 nm) 1. 286 E-10 1. 290 E-10 1. 295 E-10 1. 294 E-10 M 1 (+10 nm) 1. 282 E-10 1. 283 E-10 1. 286 E-10 1. 291 E-10 M 1 (-10 nm) 1. 274 E-10 1. 278 E-10 1. 282 E-10 1. 281 E-10 M 1 (0 nm) 1. 273 E-10 1. 277 E-10 1. 281 E-10 1. 280 E-10 1. 281 E-10 M 1 (+10 nm) 1. 273 E-10 1. 276 E-10 1. 280 E-10 Poly 1 (-10 nm) Rise Delay Variation (%) Poly 2 (-10 nm) Poly 2 (+10 nm) Poly 1(+10 nm) Poly 1 (0 nm) Poly 1(+10 nm) Contact (-10 nm) Contact (0 nm) Contact (+10 nm) Contact (-10 nm) Contact (+10 nm) M 1 (-10 nm) 0. 93 1. 32 3. 72 M 1 (0 nm) 0. 62 1. 01 3. 49 M 1 (+10 nm) 0. 70 1. 09 3. 49 M 1 (-10 nm) -0. 31 0. 08 0. 00 0. 08 0. 47 0. 39 M 1 (0 nm) -0. 31 0. 00 0. 39 0. 31 M 1 (+10 nm) -0. 62 -0. 54 -0. 31 0. 08 M 1 (-10 nm) -1. 24 -0. 93 -0. 62 -0. 70 M 1 (0 nm) -1. 32 -1. 01 -0. 70 -0. 78 -0. 70 M 1 (+10 nm) -1. 32 -1. 09 -0. 78 UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 25

DPL Options • Double Exposure • Double Patterning Resist Hardmask Target layer Resist Target layer Mask 1 Resist Hardmask Buffer oxide Hardmask Target layer Mask 1 1 st Litho-etch Exposure Mask 2 2 nd • Spacer-DP Exposure 2 nd Spacer formation • Printed Feature mask Oxide depo. CMP 2 nd etch mask positive resist negative resist Dielectric positive resist Dielectric Poly After exposure & etch Cu interconnect After Cu filling (a) Positive-tone 1 st Litho-etch Spacer removal • Photoresist Mask Poly (b) Negative-tone (a) Spaces (Trench-First) (b) Lines UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 26

Impact of Overlay in Positive DE/DP mask 1 mask 2 (misaligned to left) Positive photoresist Dielectric After exposure + etch After filling Cu Cu S 1 S 2 1 W W P’ 2 1 P’’ UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 27

Impact of Overlay in Negative DE/DP mask 1 mask 2 (misaligned to left) Negative photoresist Dielectric After exposure + etch After filling Cu S 1 Cu S 2 1 W’’ W’ P 2 P 1 S/2 UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 28

Impact of Overlay in Positive SDP Primary patterns Spacers (act as if masks) (kind of) Positive photoresist Dielectric After exposure + etch After filling Cu Cu S S 1 2 1 W’’ W P 2 1 P UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 29

Impact of Overlay in Positive SDP Primary patterns Spacers (act as if masks) (kind of ) Negative photoresist Dielectric After exposure + etch After filling Cu Cu S S 1 2 1 W’ W’ P’’ 2 1 P’ UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 30

Electrical Impacts: Capacitance Variation 15 10 5 0 -5 -10 Max increase Mean Max decrease E/ D P- P SD N P -S P- DP D E N /DP -D E/ D P- P SD N P -S D P N P- -D E/ D P -15 D Capacitance Variation (%) • Overlay error can cause more than +/- 10% capacitance variation within a die • This variation must be back-annotated to timing analysis to reduce unnecessary guardbanding M 2 M 3 M 4 M 5 UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 31

M 2 |S|/2 M 4 |S| P-DE/DP |S|/2 N-DE/DP |S|/2 P-SDP |S|/2 N-SDP UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 32

Maximum Crosstalk Induced Delay • A net has maximum crosstalk-induced delay Crosstalk Delay Variation (%) • SDP shows more sensitivity tighten overlay spec • P-DE/DP shows least sensitivity lessen overlay spec M 4 12% P-DE/DP 10% N-DE/DP P-SDP N-SDP 8% 6% 4% 2% 0% |S|/2 1 2 3 P-DE/DP M 2 N-DE/DP M 4 M 2 w/o fill M 4 P-SDP M 2 N-SDP M 4 M 2 w/o fill M 4 w/o metal fill w/ metal fill July 26 2009 UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, 33

Total Negative Slack Variation Normalized TNS (%) • SDP, especially for lower layer (smaller feature), shows more sensitivity tighter overlay spec 1, 5 1, 4 1, 3 1, 2 1, 1 1, 0 0, 9 0, 8 P-DE/DP N-DE/DP P-SDP N-SDP 1 2 3 4 5 6 7 8 UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 34