IO system Highlevel subsystems Application File System Readwrite

I/O system

High-level subsystems Application File System Read/write Block-oriented device management … … Keyboard driver Keyboard controller : : : Printer controller Network communication software … … Network driver Network controller … … devices : : : : Printer driver Open/close read/write send/receive SW/HW Hard disk controller Stream-oriented device management Network interface HW controls CD-ROW controller Hard disk drive Open/close get/put io_control interface Device dependant software CD-ROW Driver Low-level subsystems Stream device interface Device independent software I/O System Open/close I/O System Interface Block device interface Virtual memory Management

Device Controller Interface Controller Describes the operation which the driver wants the controller to carry out Driver opcode register write operand registers Indicates if controller is busy and that it cannot accept any new requests Device Indicates a ‘completed operation’ report to the driver Transfers data to and from the device busy register (boolean value) read status register data buffer read/write

Explicit Device Interface vs. Memory-mapped Interfaces 0 0 Main Memory n -1 Extension of Main Memory Controllers dev_0 opcode register dev_0 operand registers dev_1 opcode register operand registers dev_n 2 different types of instructions used to address Main Memory and Device dev_n Same format of instructions used to address Main Memory and Device

Programmed Input/Output with polling Controller opcode register operand registers 2 1 Device busy register busy status register 4 5 3 data buffer CPU 6 6 1 CPU writes operands required for input in operand registers 2 CPU writes opcode for input operation; controller executes; flag set to busy 3 Data transferred from device to data buffer 4 During data transfer in 3, CPU polls controller by testing busy flag 5 After operation completes CPU checks status register for problems 6 If no errors found, CPU transfers data from data buffer to Main Memory

Programmed Input/Output with Interrupts Controller opcode register operand registers 2 Control Logic Device busy register 1 busy status register 3 data buffer 4 5 CPU 6 6 1 CPU writes operands required for input in operand registers 2 CPU writes opcode for input operation; controller executes; flag set to busy 3 Data transferred from device to data buffer 4 Operation complete, controller issues interrupt; running pr. suspends & waiting pr. resumes 5 Resumed process checks status register for problems 6 If no errors found, process transfers data from data buffer to Main Memory

Direct Memory Access I/O (DMA) CPU overhead is high in fast devices. DMA reduces the CPU overhead in initiating and monitoring individual data transfer between device and main memory. Controller opcode register 2 operand registers Control Logic Device busy register 1 busy status register 3 5 6 CPU data buffer 4 1 CPU writes operands required for input in operand registers 2 CPU writes opcode for input operation; controller executes; flag set to busy 3 Data transferred from device to data buffer 4 Controller copies data between main memory and data buffer; (repeated) 5 After operation completes, controller resets busy flag to 0 and sends interrupt to CPU 6 CPU reads status register to check for successful operation Main Memory

DMA – CPU Cycle Stealing DMA CPU Memory CPU CTL 1 Device