Introduction to VLSI Programming Lecture 4 Data handshake

Introduction to. VLSI Programming Lecture 4: Data handshake circuits (course 2 IN 30) Prof. dr. ir. Kees van Berkel Dr. Johan Lukkien Kees van Berkel

Time table 2005 date class | lab subject Aug. 30 2 | 0 hours intro; VLSI Sep. 6 3 | 0 hours handshake circuits Sep. 13 3 | 0 hours handshake circuits Sep. 20 3 | 0 hours Tangram Sep. 27 no lecture Oct. 4 no lecture assignment Oct. 11 1 | 2 hours demo, fifos, registers | deadline assignment Oct. 18 1 | 2 hours design cases; Oct. 25 1 | 2 hours DLX introduction Nov. 1 1 | 2 hours low-cost DLX Nov. 8 1 | 2 hours high-speed DLX Nov. 29 2/13/2022 deadline final report Kees van Berkel 2

Lecture 4 Outline: • Recapitulation Lecture 3 • Data encoding; push and pull handshakes • Tangram assignment command • Handshake components: handshake latch, transferrer, multiplexer, adder • Handshake circuits & Tangram programs: fifo buffers and shift registers 2/13/2022 Kees van Berkel 3

Header: handshake circuit L=0 2/13/2022 L=1 Kees van Berkel 4

Sequencer realization ck ak ar br x cr bk Sequencer: area, delay, energy: • Area: 5 gate equivalents • Delay per cycle: 8 gate delays • Energy per cycle: 10 transitions 2/13/2022 Kees van Berkel 5

Handshake signaling and data request push channel active side ar acknowledge ak passive side data ad versus request pull channel active side ar acknowledge data ad 2/13/2022 Kees van Berkel 6

Handshake signaling: push channel time req ar ack ak early ad broad ad late ad 2/13/2022 Kees van Berkel 7

Data bundling In order to maintain event ordering at both sides of a channel, the circuit must satisfy data bundling constraint: • for push channel: delay along request wire must exceed delay of data wire; • for pull channel: delay along acknowledge wire must exceed delay of data wire. 2/13/2022 Kees van Berkel 8

Handshake signaling: pull channel When data wires are invalid: multiple and incomplete transitions allowed. req ar time ack ak early ad broad ad late ad 2/13/2022 Kees van Berkel 9

Tangram assignment x: = f(y, z) yw y f zw z xw 0 xw 1 | x xr Handshake circuit 2/13/2022 Kees van Berkel 10

Four-phase data transfer time r / b r ba / cr ca / a b c bd / cd 1 2/13/2022 2 3 Kees van Berkel 4 5 11

Handshake latch [ [ w ; [w : rd: = wd] [] r ; r ]] • 1 -bit handshake latch: w d w r rd wr rd wk = wr rk = rr 2/13/2022 Kees van Berkel w wd wr x r rd 12

N-bit handshake latch wr rr wd 1 rd 1 wd 2 rd 2 . . . wd. N wk 2/13/2022 rd. N area, delay, energy • area: 2(N+1) gate eqs. • delay per cycle: 4 gate delays • energy per write cycle: 4 + 0. 5*2 N transitions, in average rk Kees van Berkel 13

Transferrer [ [ a : (b ; c )] ; [ a : (b ; cd: = bd ; cd: = )] ] ar ak a b 2/13/2022 c br bk bd Kees van Berkel ck cr cd 14

Multiplexer [ [ a : c ; a : (cd: = ad; c ; cd: = ) [] b : c ; b : (cd: = bd; c ; cd: = ) ]] Restriction: ar br must hold at all times! 2/13/2022 Kees van Berkel a | c b 15

Multiplexer realization control circuit data circuit 2/13/2022 Kees van Berkel 16

Logic/arithmetic operator [ [ a : (b || c ) ] ; [ a : ((b || c ) ; ad: = f(bd , cd ))] ] b c f a Cheaper realization (delay sensitive): [ [ a : (b || c ) ] ; [ a : ((b || c ) ; ad: = f(bd , cd ))] ; “delay” ; ad: = ] 2/13/2022 Kees van Berkel 17

A one-place fifo buffer byte = type [0. . 255] a & BUF 1 = main proc (a? chan byte & b!chan byte). begin x: var byte | forever do a? x ; b!x od end 2/13/2022 Kees van Berkel BUF 1 b 18

A one-place fifo buffer byte = type [0. . 255] & BUF 1 = main proc (a? chan byte & b!chan byte). begin x: var byte | forever do a? x ; b!x od end a 2/13/2022 ; Kees van Berkel x b 19

2 -place buffer a BUF 1 b BUF 1 c byte = type [0. . 255] & BUF 1 = proc (a? chan byte & b!chan byte). begin x: var byte | forever do a? x ; b!x od end & BUF 2: main proc (a? chan byte & c!chan byte). begin b: chan byte | BUF 1(a, b) || BUF 1(b, c) end 2/13/2022 Kees van Berkel 20

Two-place ripple buffer 2/13/2022 Kees van Berkel 21

Two-place wagging buffer byte = type [0. . 255] & wag 2: main proc (a? chan byte & b!chan byte). begin x, y: var byte | a? x ; forever do (a? y || b!x) ; (a? x || b!y) a od end 2/13/2022 Kees van Berkel b 22

Two-place ripple register … begin x 0, x 1: var byte | forever do b!x 1 ; x 1: =x 0; a? x 0 od end 2/13/2022 Kees van Berkel 23

4 -place ripple register byte = type [0. . 255] & rip 4: main proc (a? chan byte & b!chan byte). begin x 0, x 1, x 2, x 3: var byte | forever do b!x 3 ; x 3: =x 2 ; x 2: =x 1 ; x 1: =x 0 ; a? x 0 od end 2/13/2022 Kees van Berkel 24

4 -place ripple register x 0 x 1 x 2 x 3 • area : N (Avar + Aseq ) • cycle time : Tc = (N+1) T: = • cycle energy: Ec = N E: = 2/13/2022 Kees van Berkel 25

Introducing vacancies … begin x 0, x 1, x 2, x 3, v: var byte | forever do (b!x 3 ; x 3: =x 2 ; x 2: =v) || (v: =x 1 ; x 1: =x 0 ; a? x 0) od end • what is wrong? 2/13/2022 Kees van Berkel 26

Introducing vacancies forever do ((b!x 3 ; x 3: =x 2) || (v: =x 1 ; x 1: =x 0 ; a? x 0)) ; x 2: =v od or: forever do ((b!x 3 ; x 3: =x 2) || (v: =x 1 ; x 1: =x 0)) ; (x 2: =v || a? x 0) od 2/13/2022 Kees van Berkel 27

“synchronous” 4 -p ripple register m 0 m 1 m 2 x 0 m 3 b s 0 s 1 s 2 forever do (s 0: =m 0 || s 1: =m 1 || s 2: =m 2 || b!m 3 ) ; ( a? m 0 || m 1: =s 0 || m 2: =s 1 || m 3: =s 2) od 2/13/2022 Kees van Berkel 28

4 -place wagging register x 0 x 1 a x 2 b y 0 x 2 y 1 x 3 forever do b!x 1 ; x 1: =x 0 ; a? x 0 ; b!y 1 ; y 1: =y 0 ; a? y 0 od 2/13/2022 Kees van Berkel 29

8 -place register 4 -way wagging forever do b!u 1 ; u 1: =u 0 ; a? u 0 ; b!v 1 ; v 1: =v 0 ; a? v 0 ; b!x 1 ; x 1: =x 0 ; a? x 0 ; b!y 1 ; y 1: =y 0 ; a? y 0 od 2/13/2022 Kees van Berkel 30

Four 8 8 shift registers compared 2/13/2022 Kees van Berkel 31

Next session: lecture 5 Outline: • Tangram overview • Compilation: Tangram Handshake Circuits • Tools • Demonstration • Lab work: assignment “fifos and registers” 2/13/2022 Kees van Berkel 32