Introduction to VHDL Multiplexers Discussion D 1 1

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Introduction to VHDL Multiplexers Discussion D 1. 1

Introduction to VHDL Multiplexers Discussion D 1. 1

Multiplexers A multiplexer is a digital switch 2 n inputs X(0, 2 n -1)

Multiplexers A multiplexer is a digital switch 2 n inputs X(0, 2 n -1) MUX n control lines s( 0, n-1) 1 output, Z = X(s)

Multiplexers C 0 C 1 C 2 C 3 4 x 1 MUX s

Multiplexers C 0 C 1 C 2 C 3 4 x 1 MUX s 1 s 0 Y 0 0 1 1 C 0 C 1 C 2 C 3 0 1

Multiplexers 4 x 1 MUX C 0 C 1 C 2 C 3 Y

Multiplexers 4 x 1 MUX C 0 C 1 C 2 C 3 Y s 1 s 0 0 0 s 1 s 0 Y 0 0 1 1 C 0 C 1 C 2 C 3 0 1 A multiplexer is a digital switch

Multiplexers 4 x 1 MUX C 0 C 1 C 2 C 3 Y

Multiplexers 4 x 1 MUX C 0 C 1 C 2 C 3 Y s 1 s 0 0 1 s 0 Y 0 0 1 1 C 0 C 1 C 2 C 3 0 1

Multiplexers 4 x 1 MUX C 0 C 1 C 2 C 3 Y

Multiplexers 4 x 1 MUX C 0 C 1 C 2 C 3 Y s 1 s 0 1 0 s 1 s 0 Y 0 0 1 1 C 0 C 1 C 2 C 3 0 1

Multiplexers 4 x 1 MUX C 0 C 1 C 2 C 3 Y

Multiplexers 4 x 1 MUX C 0 C 1 C 2 C 3 Y s 1 s 0 1 1 s 0 Y 0 0 1 1 C 0 C 1 C 2 C 3 0 1

A 2 x 1 MUX Behavior if (s 0 = '0') then Z :

A 2 x 1 MUX Behavior if (s 0 = '0') then Z : = A; else Z : = B; end if;

if (s 0 = A : = B : = else A : =

if (s 0 = A : = B : = else A : = B : = end if; '0') then C 0; C 2; A 4 x 1 MUX C 1; C 3; if (s 1 = '0') then if (s 0 = '0') then Z : = C 0; else Z : = C 1; end if; else if (s 0 = '0') then Z : = C 2; else Z : = C 3; end if; if (s 1 = '0') then Z : = A; else Z : = B; end if;

A 4 x 1 MUX case s is when end case; "00" "01" "10"

A 4 x 1 MUX case s is when end case; "00" "01" "10" others => => Z Z <= <= C 0; C 1; C 2; C 3;

n-line 2 -to-1 Multiplexer a(n-1: 0) b(n-1: 0) n-line 2 x 1 MUX sel

n-line 2 -to-1 Multiplexer a(n-1: 0) b(n-1: 0) n-line 2 x 1 MUX sel y(n-1: 0) sel 0 1 y a b

An n-line 2 x 1 MUX a(n-1: 0) library IEEE; use IEEE. std_logic_1164. all;

An n-line 2 x 1 MUX a(n-1: 0) library IEEE; use IEEE. std_logic_1164. all; b(n-1: 0) n-line 2 x 1 MUX y(n-1: 0) entity mux 2 g is sel generic (width: positive); port ( a: in STD_LOGIC_VECTOR(width-1 downto 0); b: in STD_LOGIC_VECTOR(width-1 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(width-1 downto 0) ); end mux 2 g;

Entity library IEEE; use IEEE. std_logic_1164. all; Each entity must begin with these library

Entity library IEEE; use IEEE. std_logic_1164. all; Each entity must begin with these library and use statements generic statement defines width of bus entity mux 2 g is generic (width: positive); port ( a: in STD_LOGIC_VECTOR(width-1 downto 0); b: in STD_LOGIC_VECTOR(width-1 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(width-1 downto 0) ); end mux 2 g; port statement defines inputs and outputs

Entity library IEEE; use IEEE. std_logic_1164. all; Mode: in or out entity mux 2

Entity library IEEE; use IEEE. std_logic_1164. all; Mode: in or out entity mux 2 g is generic (width: positive); port ( a: in STD_LOGIC_VECTOR(width-1 downto 0); b: in STD_LOGIC_VECTOR(width-1 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(width-1 downto 0) ); end mux 2 g; Data type: STD_LOGIC, STD_LOGIC_VECTOR(width-1 downto 0);

Standard Logic library IEEE; use IEEE. std_logic_1164. all; type std_ulogic is ( ‘U’, ‘X’

Standard Logic library IEEE; use IEEE. std_logic_1164. all; type std_ulogic is ( ‘U’, ‘X’ ‘ 0’ ‘ 1’ ‘Z’ ‘W’ ‘L’ ‘H’ ‘-’); -- Uninitialized -- Forcing unknown -- Forcing zero -- Forcing one -- High impedance -- Weak unknown -- Weak zero -- Weak one -- Don’t care

Standard Logic Type std_ulogic is unresolved. Resolved signals provide a mechanism for handling the

Standard Logic Type std_ulogic is unresolved. Resolved signals provide a mechanism for handling the problem of multiple output signals connected to one signal. subtype std_logic is resolved std_ulogic;

Architecture architecture mux 2 g_arch of mux 2 g is begin mux 2_1: process(a,

Architecture architecture mux 2 g_arch of mux 2 g is begin mux 2_1: process(a, b, sel) begin a(n-1: 0) if sel = '0' then y <= a; b(n-1: 0) else y <= b; end if; end process mux 2_1; end mux 2 g_arch; n-line 2 x 1 MUX y(n-1: 0) sel Note: <= is signal assignment

Architecture entity name process sensitivity architecture mux 2 g_arch of mux 2 g is

Architecture entity name process sensitivity architecture mux 2 g_arch of mux 2 g is list begin mux 2_1: process(a, b, sel) begin if sel = '0' then y <= a; else y <= b; end if; end process mux 2_1; end mux 2 g_arch; Note begin…end in architecture Sequential statements (if…then…else) must be in a process Note begin…end in process

library IEEE; use IEEE. STD_LOGIC_1164. all; use IEEE. std_logic_unsigned. all; Top-level design for Lab

library IEEE; use IEEE. STD_LOGIC_1164. all; use IEEE. std_logic_unsigned. all; Top-level design for Lab 1 entity Lab 1 is port( SW : in STD_LOGIC_VECTOR(7 downto 0); BTN 0 : in STD_LOGIC; LD : out STD_LOGIC_VECTOR(3 downto 0) ); end Lab 1;

architecture Lab 1_arch of Lab 1 is component mux 2 g generic( width :

architecture Lab 1_arch of Lab 1 is component mux 2 g generic( width : POSITIVE); port( a : in std_logic_vector((width-1) downto 0); b : in std_logic_vector((width-1) downto 0); sel : in std_logic; y : out std_logic_vector((width-1) downto 0)); end component; constant bus_width: integer : = 4; begin mux 2: mux 2 g generic map(width => bus_width) port map (a => SW(7 downto 4), b => SW(3 downto 0), sel => BTN 0, y => LD); end Lab 1_arch;

Lab 1. ucf #PACE: Start NET "BTN 0" NET "LD<0>" NET "LD<1>" NET "LD<2>"

Lab 1. ucf #PACE: Start NET "BTN 0" NET "LD<0>" NET "LD<1>" NET "LD<2>" NET "LD<3>" NET "SW<0>" NET "SW<1>" NET "SW<2>" NET "SW<3>" NET "SW<4>" NET "SW<5>" NET "SW<6>" NET "SW<7>" of PACE I/O Pin Assignments LOC = "M 13" ; LOC = "K 12" ; LOC = "P 14" ; LOC = "L 12" ; LOC = "N 14" ; LOC = "F 12" ; LOC = "G 12" ; LOC = "H 14" ; LOC = "H 13" ; LOC = "J 14" ; LOC = "J 13" ; LOC = "K 14" ; LOC = "K 13" ;

architecture Lab 1_arch of Lab 1 is component mux 2 g generic( width :

architecture Lab 1_arch of Lab 1 is component mux 2 g generic( width : POSITIVE); port( a : in std_logic_vector((width-1) downto 0); b : in std_logic_vector((width-1) downto 0); sel : in std_logic; y : out std_logic_vector((width-1) downto 0)); end component; begin constant bus_width: integer : = 4; mux 2: mux 2 g generic map(width => bus_width) port map (a => SW(7 downto 4), b => SW(3 downto 0), sel => BTN 0, y => LD); end Lab 1_arch;

An n-line 4 x 1 multiplexer a(n-1: 0) b(n-1 : 0) c(n-1 : 0)

An n-line 4 x 1 multiplexer a(n-1: 0) b(n-1 : 0) c(n-1 : 0) d(n-1 : 0) 8 -line 4 x 1 MUX sel(1: 0) y(n-1 : 0) Sel “ 00” “ 01” “ 10” “ 11” y a b c d

An 8 -line 4 x 1 multiplexer library IEEE; use IEEE. std_logic_1164. all; entity

An 8 -line 4 x 1 multiplexer library IEEE; use IEEE. std_logic_1164. all; entity mux 4 g is generic(width: positive : = 8); port ( a: in STD_LOGIC_VECTOR (width-1 downto 0); b: in STD_LOGIC_VECTOR (width-1 downto 0); c: in STD_LOGIC_VECTOR (width-1 downto 0); d: in STD_LOGIC_VECTOR (width-1 downto 0); sel: in STD_LOGIC_VECTOR (1 downto 0); y: out STD_LOGIC_VECTOR (width-1 downto 0) ); end mux 4 g;

Example of case statement architecture mux 4 g_arch of mux 4 g is begin

Example of case statement architecture mux 4 g_arch of mux 4 g is begin Note implies operator => process (sel, a, b, c, d) begin case sel is Sel y when "00" => y <= a; “ 00” a when "01" => y <= b; “ 01” b when "10" => y <= c; when others => y <= d; “ 10” c end case; “ 11” d end process; end mux 4 g_arch; Must include ALL possibilities in case statement

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