INTRODUCTION TO VERILOG AND ALCHITRY Eric Prebys P

INTRODUCTION TO VERILOG AND ALCHITRY Eric Prebys

P 116 B - Winter 2020 P 116 B - Intro to Verilog and Alchitry 2 Background: VHDL and Verilog • Two major HDL languages are used to design ASICs and configure FPGAs • (Very High Speed IC) Hardware Description Language (VHDL) • Began in 1983 by the Do. D as a way to specify the behavior of ASICs to vendors • Based on Ada programming language, also a Do. D product • Became IEEE standard 1076 in 1987 • Verilog • Created in industry in 1983 as a way to simulate ASICs • Based on the C programming language • Became IEEE standard 1364 in 1995 • Both became adopted as ways to design ASICs and configure FPGAs

P 116 B - Winter 2020 P 116 B - Intro to Verilog and Alchitry Example: 8 -bit counter and AND gate 3

P 116 B - Winter 2020 P 116 B - Intro to Verilog and Alchitry 4 VHDL Implementation Explicitly include libraries Separately define “entity” and “architecture” (can have multiple architectures for each entity) Concurrent statements Process statements (interpreted sequentially) Can only do math with number types! Must explicitly convert between data types!

P 116 B - Winter 2020 P 116 B - Intro to Verilog and Alchitry 5 Verilog Implementation Everything in a single “module” Concurrent statements “always” block (interpreted sequentially) Can mix mathematical and logical operations!

P 116 B - Winter 2020 P 116 B - Intro to Verilog and Alchitry 6 Comparison of VHDL and Verilog • VHDL • Pros • Strongly typed • Takes more work to get it to compile • More likely to work once it does • Lots of programming constructs, resources, and separate data types • Example: enumerated type for state machines • Fully “deterministic” (behavior always independent of compiler) • Case insensitive (I consider this a “pro”) • Cons • Verbose • Based on largely defunct languages (Pascal and Ada), so not familiar to most people • Verilog • Pros • Compact and concise • Syntax similar to C/C++, so more familiar to most people • Cons • Weakly typed, and otherwise very “forgiving” • Quicker to compile • Might not do what’s expected • Fewer data types and resources • State machines are particularly clunky • Determinism only insured through good coding practices! • Case sensitive

P 116 B - Winter 2020 P 116 B - Intro to Verilog and Alchitry Popularity Based on Google Searches 7

P 116 B - Winter 2020 P 116 B - Intro to Verilog and Alchitry 8 Bottom Line • Both VHDL and Verilog can get the job done • Both have ~equal user communities • Very few problems that can’t be solved with Google. • Once you grasp the logical basis of one HDL, it’s straightforward to learn another. • Note: individual modules are compatible at the interface (pin) level. Different parts of a single design can incorporate VHDL, Verilog, schematic capture, or other design tools.

P 116 B - Winter 2020 P 116 B - Intro to Verilog and Alchitry 9 Switching from VHDL to Verilog for P 116 B • For several years, this course had one FPGA lab, and used VHDL. • I expanded the FPGA content, but continued to use VHDL through last year. • After investigating the matter, I’ve decided to switch to Verilog for the following reasons: • Because of its similarity to C and simpler syntax, the learning curve is much faster, so we can more quickly go from learning about the language to using it. • I think the “philosophy” is easier to understand than VHDL • Specifically, we’ll use Verilog-2001, which has some features not included in earlier versions • Caveat: The FPGA labs are entirely new this year • New boards • New language • New projects • There will be some glitches!

P 116 B - Winter 2020 P 116 B - Intro to Verilog and Alchitry 10 Major Differences with C • Much of the syntax in Verilog is very similar to C, as regards mathematical and logical statements • There are many small differences, but the three that will probably annoy you the most if you are a C/C++ programmer are… • One necessary annoying difference • The distinction between “bit vectors” and “arrays” (more about this shortly) • Two unnecessarily annoying differences • Most cases where C uses open and close curly brackets (“{” ”}”), Verilog will use “begin” and “end” • Verilog doesn’t have the “++” or the “--” operators (even though they would really come in handy!)

P 116 B - Winter 2020 P 116 B - Intro to Verilog and Alchitry 11 Use of Verilog in 116 B • Our goal is to teach you the minimum amount of Verilog needed to do the FPGA-based labs. • In particular, we will not spend very much time on simulation, which is one of the most powerful features of Verilog • For the simple circuits we’ll be designing, it’s literally easier to download it and test it directly than it is to set up and interpret a simulation.

P 116 B - Winter 2020 P 116 B - Intro to Verilog and Alchitry Parts of a Verilog Module 12

P 116 B - Winter 2020 P 116 B - Intro to Verilog and Alchitry 13 Module Interface (“pins”) • Three types of interface pins (self-explanatory) • input • output • inout • All methods of design entry are compatible at this level, so different modules may be • Verilog • VHDL • Other HDL • Schematic capture • GUI/parametric design tools (e. g. “wizards”)

P 116 B - Winter 2020 P 116 B - Intro to Verilog and Alchitry Order of statements • Order only matters in the interface and inside “always” blocks • This code would behave exactly like the previous example 14

P 116 B - Winter 2020 P 116 B - Intro to Verilog and Alchitry 15 Nets • Nets are used to connect one thing to another. • Like wires connecting one part to another • For the most part, they are used outside of always blocks. • Order does not matter • They have no “memory” • The two types you will use mostly are We’ll use mostly this • wire: just what it sounds like. Can have one and only one driver. • tri: can have multiple driving sources, with at most one being driven at a time (the rest are high-Z) • Others that are less common, and we won’t use • supply 0, supply 1, triand, trior, tri 0, tri 1, wand, wor • There also “strength modifiers”, which we won’t use

P 116 B - Winter 2020 P 116 B - Intro to Verilog and Alchitry 16 Variables • Unlike nets, variables can retain data, and generally serve three purposes • Specify complex logical operations (details might be optimized away) • Represent data stored in flip-flops at clock cycles • Perform calculations related to simulations • Types of variables We’ll use mostly this for “genuine” signals • reg – one bit logical variable • integer – 32 -bit 2 s complement signed integer Loop counters, etc • real – 64 -bit IEEE floating point number • time – type or real used for storing time • realtime – 64 -bit unsigned integer used to keep track of time during simulation

P 116 B - Winter 2020 P 116 B - Intro to Verilog and Alchitry 17 Bit vectors vs. arrays • wire and reg are single-bit entities • We can turn them into bit vectors by declaring a dimension before the name. • We can create multiple dimension arrays by specifying the dimension after the name. • Examples • Single 8 -bit wire vector • wire [7: 0] name; • element = name[i]; • Array of single bits • reg name [7: 0]; • element = name [i]; • Array of 8 -bit vectors • reg [7: 0] name [7: 0]; • element = name[i][j]; • Pro tip: accidentally putting the bit-vector dimension after the name is a common error that will be hard to catch.

P 116 B - Winter 2020 P 116 B - Intro to Verilog and Alchitry 18 Specifying constants in Verilog • By default, numbers are interpreted as 2 s complement signed integers • Otherwise, numbers are specified as n’tdddd, where • n=number of bits • t=type code • D or d: decimal • H or h: hexadecimal • O or o: octal • B or B: binary • dddd are the digits • Note: In general, Varilog will NOT check that the sizes on the LHS and RHS match! (big difference from VHDL)

P 116 B - Winter 2020 19 P 116 B - Intro to Verilog and Alchitry Operators in Verilog • These operators operate on whole words and are identical to C* operations logical tests *tables from “Verilog” presentation by Mohamad Rayan

P 116 B - Winter 2020 P 116 B - Intro to Verilog and Alchitry Operators (cont’d) • Bitwise operations (some like C, some different) 20

P 116 B - Winter 2020 P 116 B - Intro to Verilog and Alchitry 21 Sub-vectors and concatenation • Can select sub-vectors, by referencing the appropriate index range, and can concatenate vectors using the {} concatenation operator. • Special bit values • x: “don’t care”, as a logical test • z: “high-impedance”, for a tri-state output

P 116 B - Winter 2020 P 116 B - Intro to Verilog and Alchitry 22 Concurrent Statement vs. Always blocks • Think of “concurrent” statements as “soldering a wire” from one point to the other. • The are outside of “always” blocks, and order doesn’t matter • “always” blocks are interpreted sequentially • Take effect, based on the “sensitivity” list • Variables (reg, etc) can only be set inside always blocks!

P 116 B - Winter 2020 P 116 B - Intro to Verilog and Alchitry 23 Concurrent Statements • Concurrent statements are executed outside of procedural (always) blocks. • The are executed concurrently and order doesn’t matter. • They may include • Basic assignments with mathematical or logical operations. • Conditional assignments • Functions (we’ll get to these) • Instantiations of other designs (we’ll also get to these)

P 116 B - Winter 2020 P 116 B - Intro to Verilog and Alchitry 24 Procedural (always) Blocks • always blocks contain more complex operations and/or synchronous (clocked) operations • They are interpreted sequentially, but may not execute sequentially! • In addition to logical and mathematical and logical operations, always blocks can contain • if-then-else blocks • for loops • case blocks • They can contain functions and tasks (discussed shortly). • They cannot contain instantiations • Generally, always, if-then-else, for, and case include either • The single line following them, or • Multiple lines bracketed by begin and end (like “{“ and “}” in C or Java)

P 116 B - Winter 2020 P 116 B - Intro to Verilog and Alchitry 25 Structures in always blocks (a lot like C/Java) • if-then-else • for • case Doesn’t understand i++

P 116 B - Winter 2020 P 116 B - Intro to Verilog and Alchitry 26 always block sensitivity list • always blocks are executed based on the sensitivities in the header • Synchronous vs asynchronous execution • What’s the difference in behavior between the following two examples?

P 116 B - Winter 2020 P 116 B - Intro to Verilog and Alchitry 27 Assignment of Signals • Because of the different nature of concurrent and procedural statements, there are important differences in how signals may be used in different circumstance • Module interface • nets: inputs, outputs, or inouts • variables: outputs only • Concurrent statements • nets: LHS or RHS of equations • variables: RHS only • Procedural statements • nets: RHS only • variables: LHS or RHS of equations

P 116 B - Winter 2020 Optimization Example P 116 B - Intro to Verilog and Alchitry Will not exist after compilation • Consider the following code What the code says 28 What’s synthesized

P 116 B - Winter 2020 P 116 B - Intro to Verilog and Alchitry Revisiting our counter code… 29

P 116 B - Winter 2020 P 116 B - Intro to Verilog and Alchitry 30 Blocking vs. non-blocking statements • In all our examples up until now, we have used “=“ in always blocks. These are referred to as “blocking” statements, which are • Are interpreted sequentially, and the value on the RHS will have any modifications made in previous statements or even in other always blocks triggered by the same event. • If simulation delays are present, delays will be implemented sequentially (i. e. one line “blocks” the next) • On the other hand, statements that use the “<=“ equality are referred to as “Non-blocking statements”. • The value on the RHS will retain the value it had before the trigger event, regardless of previous lines • Non-blocking lines are interpreted concurrently by simulations.

P 116 B - Winter 2020 P 116 B - Intro to Verilog and Alchitry 31 Usage of non-blocking Statements • Consider the following two examples. What will be the values of A and B after the first clock? • Blocking example • Non-blocking example

P 116 B - Winter 2020 P 116 B - Intro to Verilog and Alchitry 32 Non-determinism • In VHDL, variables are defined within procedural blocks and may only be used in the blocks in which they are defined. • In Verilog, variables are defined globally within the module, and may be used in multiple always blocks, which can lead to problems • Example: • R=0 when the first clock cycle comes • What does A equal after the clock? • Answer: it depends on the compiler • Only good coding practices will prevent unpredictability

P 116 B - Winter 2020 P 116 B - Intro to Verilog and Alchitry 33 Instantiation • One module can be “instantiated” one or more times in another module • Instantiated module could be in a library, designed using different design tools (VHDL, schematic capture, etc) • This process may be nested to any level • Instantiations can only occur in concurrent section! • Signals are made either by order or name (I like to do it by name in the correct order) Name of instantiated module (might be in a library) Unique instance name Argument list

P 116 B - Winter 2020 P 116 B - Intro to Verilog and Alchitry 34 Functions • Functions are defined (or included inside modules), and can simplify repetitive • • tasks. They have one or more inputs and one and only one output. They may be used any number of times, in both concurrent sections and procedural sections. Functions can call other functions They cannot non-blocking statements!

P 116 B - Winter 2020 P 116 B - Intro to Verilog and Alchitry 35 Tasks • Like functions, tasks are defined inside the module • They can contain multiple inputs and outputs, based on the named calling variables. • They can only be used inside procedural blocks. • They may call other functions or tasks

P 116 B - Winter 2020 P 116 B - Intro to Verilog and Alchitry 36 Parameters • Because FPGA configurations are synthesized at compilation time, many things can’t be done with variables: in particular, bit ranges or array dimensions. • These can be done with named parameters, for example • Parameters may also have default values in modules that can be overridden at instantiation time as follows. For example, in the 24 -bit counter you made in this week’s lab, you could define the header as but then override it and make it a 16 -bit counter for (spoiler) the next lab during instantiation with • Parameters may be set to other parameters, or mathematical operations involving other parameters and/or constants, but ultimately everything must resolve to a constant at compilation time!