Introduction to SystemLevel Modeling in System C 2

Introduction to System-Level Modeling in System. C 2. 0 Part of HW/SW Codesign of Embedded Systems Course (CE 40 -226) 14/06/43 Winter. Spring 2001 Codesign of Embedded Systems 1

Topics n n A Brief Review of System. C 1. 0 Objectives of System. C 2. 0 Communication and Synchronization in System. C 2. 0 Models of Computation within System. C Winter-Spring 2001 Codesign of Embedded Systems 2

Introduction to System-Level Modeling in System. C 2. 0 A Brief Review of System. C 1. 0 14/06/43 Winter. Spring 2001 Codesign of Embedded Systems 3

Brief Review of System. C 1. 0 n n n A set of modeling constructs in RTL or Behavioral abstraction level Structural design using Modules, Ports, and Signals Rich set of data types including bit-true types n Specially: Fixed-Point data types for DSP apps. Winter-Spring 2001 Codesign of Embedded Systems 4

Brief Review of System. C 1. 0 (cont’d) n Concurrent Behavior is described using Processes n n Processes can suspend and resume execution Limited control over awakening events n n Events and sensitivity list are static (compile-time specified) SC_THREAD and SC_CTHREAD processes n n n Can suspend and resume execution Require their own execution stack Memory and Context-switching time overhead Winter-Spring 2001 Codesign of Embedded Systems 5

Brief Review of System. C 1. 0 (cont’d) n Hardware Signals are hard to model in software n Initialization to X n n n Multiple drivers n n Used to detect reset problems sc_logic, sc_lv data types resolved logic signals Not immediately change their output value n Capability of swapping two regs on clock edge Winter-Spring 2001 Codesign of Embedded Systems 6

Brief Review of System. C 1. 0 (cont’d) n Delayed assignment and delta cycles n n Just like VHDL and Verilog Essential to properly model hardware signal assignments n n n Each assignment to a signal won’t be seen by other processes until the next delta cycle Delta cycles don’t increase user-visible time Multiple delta cycles may occur Winter-Spring 2001 Codesign of Embedded Systems 7

Introduction to System-Level Modeling in System. C 2. 0 Objectives of System. C 2. 0 14/06/43 Winter. Spring 2001 Codesign of Embedded Systems 8

Objectives of System. C 2. 0 n Primary goal: Enable System-Level Modeling n n Systems include hardware and software Challenge: n n n Wide range of design models of computation Wide range of design abstraction levels Wide range of design methodologies Winter-Spring 2001 Codesign of Embedded Systems 9

Objectives of System. C 2. 0 (cont’d) n System. C 2. 0 n n Introduces a small but very general purpose modeling foundation => Core Language Support for other models of computation, methodologies, etc n They are built on top of the core language, hence are separate from it n Even System. C 1. 0 Signals are built on top of this core in n Winter-Spring 2001 System. C 2. 0 Other library models are provided: n FIFO, Timers, . . . Codesign of Embedded Systems 10

Introduction to System-Level Modeling in System. C 2. 0 Communication and Synchronization in System. C 2. 0 14/06/43 Winter. Spring 2001 Codesign of Embedded Systems 11

Communication and Synchronization n n System. C 1. 0 Modules and Processes are still useful in system design But communication and synchronization mechanisms in System. C 1. 0 (Signals) are restrictive for system-level modeling n n Communication using queues Synchronization (access to shared data) using mutexes Winter-Spring 2001 Codesign of Embedded Systems 12

Communication and Synchronization (cont’d) n System. C 2. 0 introduces general-purpose n Channels n n n Interfaces n n A container class for communication and synchronization They implement one or more interfaces Specify a set of access methods to the channel Events n n Flexible, low-level synchronization primitive Used to construct other forms of synchronization Winter-Spring 2001 Codesign of Embedded Systems 13

Communication and Synchronization (cont’d) n Other comm & sync models can be built based on the above primitives n Examples n HW-signals, queues (FIFO, LIFO, message queues, etc) semaphores, memories and busses (both at RTL and transaction-based models) Winter-Spring 2001 Codesign of Embedded Systems 14

Third Quiz n Design a FIFO of 8 characters, along with a producer and a consumer process, communicating through the FIFO Winter-Spring 2001 Codesign of Embedded Systems 15

Communication and Synchronization (cont’d) Interfaces Module 1 Module 2 Channel Events Ports to Interfaces Winter-Spring 2001 Codesign of Embedded Systems 16

A Communication Modeling Example: FIFO Producer Write Interface Consumer FIFO Read Interface Winter-Spring 2001 Codesign of Embedded Systems 17

p c FIFO Example: Declaration of Interfaces class write_if : public sc_interface { public: virtual void write(char) = 0; virtual void reset() = 0; }; class read_if : public sc_interface { public: virtual void read(char&) = 0; virtual int num_available() = 0; }; Winter-Spring 2001 Codesign of Embedded Systems 18

p c FIFO Example: Declaration of FIFO channel class fifo: public sc_channel, public write_if, public read_if { private: enum e {max_elements=10}; char data[max_elements]; int num_elements, first; sc_event write_event, read_event; bool fifo_empty() {…}; bool fifo_full() {…}; public: fifo() : num_elements(0), first(0); Winter-Spring 2001 void write(char c) { if (fifo_full()) wait(read_event); data[ <you calculate> ] = c; ++num_elements; write_event. notify(); } void read(char &c) { if (fifo_empty()) wait(write_event); c = data[first]; --num_elements; first = …; read_event. notify(); } Codesign of Embedded Systems 19

Declaration of p c FIFO channel (cont’d) void reset() { num_elements = first = 0; { int num_available() { return num_elements; { //; { end of class declarations Winter-Spring 2001 Codesign of Embedded Systems 20

FIFO Example (cont’d) n Any channel must n n n be derived from sc_channel class be derived from one (or more) classes derived from sc_interface provide implementations for all pure virtual functions defined in its parent interfaces Winter-Spring 2001 Codesign of Embedded Systems 21

FIFO Example (cont’d) n Note the following extensions beyond System. C 1. 0 n wait() call n n wait(sc_event) => dynamic sensitivity wait(time) wait(time_out, sc_event) Events n n are the fundamental synchronization primitive have no type, no value always cause sensitive processes to be resumed can be specified to occur: n immediately/ one delta-step later/ some specific time later Winter-Spring 2001 Codesign of Embedded Systems 22

p Completing the Comm. Modeling Example SC_MODULE(producer) { public: sc_port<write_if> out; FIFO SC_MODULE(consumer) { public: sc_port<read_if> in; SC_CTOR(producer) { SC_THREAD(main); } SC_CTOR(consumer) { SC_THREAD(main); } void main() { char c; while (true) { out. write(c); if(…) out. reset(); } } void main() { char c; while (true) { in. read(c); cout<< }; c in. num_available(); } } }; Winter-Spring 2001 Codesign of Embedded Systems 23

p c Completing the Comm. FIFO Modeling Example (cont’d) SC_MODULE(top) { public: fifo afifo; producer *pproducer; consumer *pconsumer; SC_CTOR(top) { pproducer=new producer(“Producer”); pproducer->out(afifo); pconsumer=new consumer(“Consumer”); pconsumer->in(afifo); }; Winter-Spring 2001 Codesign of Embedded Systems 24

Completing the Comm. Modeling Example (cont’d) n Note: n Producer module n sc_port<write_if> out; n n Consumer module n sc_port<read_if> in; n n Producer can only call member functions of write_if interface Consumer can only call member functions of read_if interface Producer and consumer are n n unaware of how the channel works just aware of their respective interfaces Channel implementation is hidden from communicating modules Winter-Spring 2001 Codesign of Embedded Systems n 25

Completing the Comm. Modeling Example (cont’d) n Advantages of separating communication from functionality n n Trying different communication modules Refine the FIFO into a software implementation n n Using queuing mechanisms of the underlying RTOS Refine the FIFO into a hardware implementation n Channels can contain other channels and modules n n n Winter-Spring 2001 Instantiate the hw FIFO module within FIFO channel Implement read and write interface methods to properly work with the hw FIFO Refine read and write interface methods by inlining them into producer and consumer codes Codesign of Embedded Systems 26

Introduction to System-Level Modeling in System. C 2. 0 Models of Computation within System. C 14/06/43 Winter. Spring 2001 Codesign of Embedded Systems 27

Models of Computation within System. C n Many different models n n The best choice is not always clear Basic topics in a computation model n The model of time, and event ordering constraints n n Time model: real valued, integer-valued, untimed Event ordering: globally ordered, partially ordered Supported methods of communication between concurrent processes Rules for process activation Winter-Spring 2001 Codesign of Embedded Systems 28

Models of Computation within System. C (cont’d) n System. C 2. 0 n Generic model of computation n n The designer is to implement his desired model (Virtually) all discrete-time models are supported n n n Static Multi-rate Data-flow Dynamic Multi-rate Data-flow Kahn Process Networks Communicating Sequential Processes Discrete Event as used for n n n RTL hardware modeling network modeling (e. g. stochastic or “waiting room” models) transaction-based So. C platform-modeling Winter-Spring 2001 Codesign of Embedded Systems 29

Models of Computation within System. C (cont’d) n Proof of generic usage of System. C 2. 0 primitives n n Signals are realized on top of channels, interfaces, and events System. C 2. 0 is not suitable for continuoustime models (e. g. analog modeling( Winter-Spring 2001 Codesign of Embedded Systems 30

What we learned today n n System. C 2. 0 new features vs. System. C 1. 0 System. C 2. 0 approach to system-level modeling n n Separation of communication from functionality Providing designer with basic tools to implement his desired model of computation Winter-Spring 2001 Codesign of Embedded Systems 31

Complementary notes: Assignments n Take Assignment 7 n Due Date: Saturday, Khordad 5 th Winter-Spring 2001 Codesign of Embedded Systems 32