Introduction to Microelectronic Fabrication by Richard C Jaeger

Introduction to Microelectronic Fabrication by Richard C. Jaeger Distinguished University Professor ECE Department Auburn University Chapter 8 Packaging and Yield © 2002 Pearson Education, Inc. , Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN 0 -201 -44494 -1.

Copyright Notice • © 2002 Pearson Education, Inc. , Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. • For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN 0 -201 -44494 -1. © 2002 Pearson Education, Inc. , Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN 0 -201 -44494 -1.

Packaging Processed Silicon Wafer • 150 -mm wafer ready • Mounted on screen ready for dicing saw • Dice on wafer tested by probing prior to mounting • Good dice will then be packaged © 2002 Pearson Education, Inc. , Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN 0 -201 -44494 -1.

Packaging Bonding Pad Configurations (a)Peripheral Bonding Pads (b)Area Array Bonding Pads Range from 125 m x 125 m down to 25 m x 25 m © 2002 Pearson Education, Inc. , Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN 0 -201 -44494 -1.

Packaging “TO-Style” and Inline © 2002 Pearson Education, Inc. , Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN 0 -201 -44494 -1.

Packaging Gold Wire Bonding (a) (c) Figure 8. 3 (a) An SEM of gold ball bonding (b) SEM of high density gold ball bonding (c) SEM of bonded die. Courtesy of Kulicke and Soffa Industries, Inc. (K&S). (b) © 2002 Pearson Education, Inc. , Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN 0 -201 -44494 -1.

Packaging Themosonic Ball-Wedge Bonding © 2002 Pearson Education, Inc. , Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN 0 -201 -44494 -1.

Packaging Ultrasonic Bonding © 2002 Pearson Education, Inc. , Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN 0 -201 -44494 -1.

Packaging Pin Grid Array • Pin Grid Array (PGA) Package with Upward Facing Cavity • PGAs also come with the Cavity Facing Downward Figure 8. 7 © 2002 Pearson Education, Inc. , Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN 0 -201 -44494 -1.

Packaging Leadless Chip Carriers Figure 8. 8 (a) Ceramic leadless chip carriers with top connections. (b) LCC with edge connections in grooves on the side of the package. © 2002 Pearson Education, Inc. , Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN 0 -201 -44494 -1.

Packaging Plastic Packaging Gull wing surface mount J-lead surface mount Through hole Surface Mount © 2002 Pearson Education, Inc. , Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN 0 -201 -44494 -1.

Packaging Solder Ball Formation • Layers of chrome, copper, lead and tin are sequentially deposited • After heating for reflow, the 5% tin 95% lead solder ball forms © 2002 Pearson Education, Inc. , Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN 0 -201 -44494 -1.

Packaging Solder Balls - Area Array (a) (b) Figure 8. 10 (a) Cross section through a solder ball before and after reflowing. Copyright 1969 by International Business Machines Corporation. Reprinted with permission from Ref. [4]. (b) Flip-chip Pb/Sn solder bumps in standard 250 m pitch (right) and 50 m. Courtesy of MCNC Optical and Electronic Packaging Group. © 2002 Pearson Education, Inc. , Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN 0 -201 -44494 -1.

Packaging Solder Bumps Figure 8. 11 Bumps formed by modification of the wirebond process. Courtesy of Kulicke and Soffa Industiries, Inc. (K&S). © 2002 Pearson Education, Inc. , Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN 0 -201 -44494 -1.

Packaging Ball Grid Array Figure 8. 12 (a) Ball grid array cross section (b) Intel microprocessor using a BGA. Courtesy of Intel Corp. © 2002 Pearson Education, Inc. , Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN 0 -201 -44494 -1.

Packaging Gold Bumps on Aluminum © 2002 Pearson Education, Inc. , Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN 0 -201 -44494 -1.

Packaging Tape Automated Bonding © 2002 Pearson Education, Inc. , Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN 0 -201 -44494 -1.

Packaging Chip Scale Packages Figure 8. 15 (a) Chip scale package using wire bonding (b) Alternate form of CSP (c) Chip-on-board packaging © 2002 Pearson Education, Inc. , Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN 0 -201 -44494 -1.

Yield versus Area Figure 8. 16 Illustration of wafers showing effect of die size on yield. Dots indicate the presence of a defective die location. (Die are inked at test. ) (a) For a particular die size, yield is 43%. (b) If the die size were doubled, the yield would be only 22% © 2002 Pearson Education, Inc. , Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN 0 -201 -44494 -1.

Yield Modeling Possible Defect Distributions Figure 8. 17 (a) Impulse where every wafer has exactly the same number of defects (b) A triangular approximation to a Gaussian density (c) A uniform density function © 2002 Pearson Education, Inc. , Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN 0 -201 -44494 -1.

Yield Modeling Theory • ITRS 2010 (a = 5) – D 0 ≤ 0. 1/cm 2 – Critical Defect Size < 30 nm © 2002 Pearson Education, Inc. , Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN 0 -201 -44494 -1.

Yield Modeling Yield Curves • Theoretical yield curves versus defect density - area product • Yield drops off rapidly as die area increases, but not as rapidly as Poisson distribution predicts • Early predictions were based upon Y = exp(D 0 A). Fortunately, this result was far too pessimistic. Figure 8. 18 © 2002 Pearson Education, Inc. , Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. ITRS Assumption For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN 0 -201 -44494 -1.

Packaging and Yield References © 2002 Pearson Education, Inc. , Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN 0 -201 -44494 -1.

End of Chapter 8 © 2002 Pearson Education, Inc. , Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN 0 -201 -44494 -1.