Introduction to Logic Synthesis Alan Mishchenko UC Berkeley

Overview l (1) Problems in logic synthesis l l (2) And-Inverter Graphs (AIGs) l l Representations and computations The foundation of innovative synthesis (3) AIG-based solutions l Synthesis, mapping, verification 2

(1) Problems In Synthesis l What are the objects to be “synthesized”? l l l How to represent them efficiently? l l l Boolean functions (with or without don’t-cares) State machines, relations, sets, etc Depends on the task to be solved Depends on the size of an object How to create, transform, minimize the representations? l l l Multi-level logic synthesis Technology mapping Verification 3

Terminology l Logic function (e. g. F = ab+cd) l l Variables (e. g. b) Minterms (e. g. abcd) Cube (e. g. ab) Logic network l l l Primary inputs/outputs Logic nodes Fanins/fanouts Transitive fanin/fanout cone Cut and window (defined later) Primary outputs TFO Fanouts Fanins TFI Primary inputs 4

Logic (Boolean) Function ab l cd Completely specified logic function 00 01 11 10 00 0 0 1 0 11 1 1 10 0 0 1 0 00 01 11 10 00 0 0 1 0 01 0 11 1 10 0 0 1 0 ab l cd Incompletely specified logic function 00 01 11 10 00 0 0 11 1 1 10 0 0 00 01 11 10 00 0 0 01 0 1 1 1 0 0 11 0 0 0 1 10 0 0 00 01 11 10 00 1 1 0 01 1 0 0 1 0 10 1 1 On-set Off-set DC-set 5

Relations l Relation (a 1, a 2) (b 1, b 2) l l l (0, 0) (0, 1) (1, 0)(0, 1) (1, 0) (1, 1) (1, 0) Characteristic function a 1 a 2 b 1 b 2 FSM 00 01 11 10 00 1 0 01 0 0 11 0 0 0 1 1 0 00 01 11 10 00 1 1 0 01 1 11 10 1 0 0 Current state 00 01 10 Next state 6

Representation Zoo Find each of these representations? l l l F Truth table (TT) Sum-of-products (SOP) Product-of-sums (POS) Binary decision diagram (BDD) And-inverter graph (AIG) Logic network (LN) F a b c d a F F = ab+cd x+ cd b c ab d F = (a+c)(a+d)(b+c)(b+d) a 0 1 b c d abcd F 0000 0 0001 0 0010 0 0011 1 0100 0 0101 0 0110 0 0111 1 1000 0 1001 0 1010 0 1011 1 1100 1 1101 1 1110 1 1111 1 7

Representation Overview l TT are the natural representation of logic functions l l l SOP is widely used in synthesis tools since 1980’s l l l More compact than TT, but not canonical Can be efficiently minimized (SOP minimization by Espresso, ISOP computation) and translated into multi-level forms (algebraic factoring) BDD is a useful representation discovered around 1986 l l Not practical for large functions Still good for functions up to 16 variables Canonical (for a given function, there is only one BDD) Very good, but only if (a) it can be constructed, (b) it is not too large Unreliable (non-robust) for many industrial circuits AIG is an up-and-coming representation! l l l Compact, easy to construct, can be made “canonical” using a SAT solver Unifies the synthesis/mapping/verification flow The main reason to give this talk 8

Historical Perspective Problem Size ABC 100000 SIS, VIS, MVSIS 100 Espresso, MIS, SIS 50 16 TT 1950 -1970 SOP 1980 AIG CNF BDD 1990 2000 Time 9

What Representation to Use? l For small functions (up to 16 inputs) l l TT works the best (local transforms, decomposition, factoring, etc) For medium-sized functions (16 -100 inputs) l l In some cases, BDDs are still used (reachability analysis) Typically, it is better to represent as AIGs l Translate AIG into CNF and use SAT solver for logic manipulation l l Interpolate or enumerate SAT assignments For large industrial circuits (>100 inputs, >10, 000 gates) l l Traditional LN representation is not efficient AIGs work remarkably well l l Lead to efficient synthesis Are a natural representation for technology mapping Easy to translate into CNF for SAT solving etc 10

What are Typical Transformations? l Typical transformations of representations l l For SOP, minimize cubes/literals For BDD, minimize nodes/width For AIG, restructure, minimize nodes/levels For LN, restructure, minimize area/delay 11

Computations in Networks / AIGs l Divide-and-conquer l l Guess-and-check l l Traversal, windowing, cut computation Bit-wise simulation Reason-and-prove l Boolean satisfiability 12

Traversal l Traversal is visiting nodes in the network in some order Primary outputs 8 l Topological order visits nodes from PIs to POs l Each node is visited after its fanins are visited 7 3 6 2 1 l Reverse topological order visits nodes from POs to PIs l Each node is visited after its fanouts are visited 5 4 Primary inputs Traversal in a topological order 13

Windowing l Definition l l A window for a node is the node’s context, in which an operation is performed A window includes l l l k levels of the TFI m levels of the TFO all re-convergent paths between window PIs and window POs Window POs m=3 Pivot node k=3 Window PIs 14

Structural Cuts in AIG n A cut of a node n is a set of nodes in transitive fan-in such that every path from the node to PIs is blocked by nodes in the cut. A k-feasible cut means the size of the cut must be k or less. p a q b c The set {p, b, c} is a 3 -feasible cut of node n. (It is also a 4 -feasible cut. ) k-feasible cuts are important in FPGA mapping because the logic between root n and the cut nodes {p, b, c} can be replaced by a k-LUT 15

Cut Computation { {n}, {p, q}, {p, b, c}, {a, b, q}, {a, b, c} } n { {p}, {a, b} } { {q}, {b, c} } p Computation is done bottom-up { {a} } a q { {b} } b { {c} } k Cuts per node 4 6 5 20 6 80 7 150 c The set of cuts of a node is a ‘cross product’ of the sets of cuts of its children. Any cut that is of size greater than k is discarded. (P. Pan et al, FPGA ’ 98; J. Cong et al, FPGA ’ 99) 16

Bitwise Simulation l Assign particular (or random) values at the primary inputs l l Perform bitwise simulation at each node l l Multiple simulation patterns are packed into 32 - or 64 -bit strings Nodes are ordered in a topological order l l The uniformity of AND-nodes Speed of bitwise simulation Topological ordering of memory used for simulation information 0 2 0 3 1 4 1 F 1 0 2 0 3 0 3 1 4 0 Works well for AIG due to l 1 a b c d 1 0 1 2 1 0 0 0 3 1 0 1 1 4 1 1 0 1 17

Boolean Satisfiability l Given a CNF formula (x), satisfiability problem is to prove that (x) 0, or to find a counter-example x’ such that (x’) 1 l Why this problem arises? l l If CNF were a canonical representation (like BDD), it would be trivial to answer this question. But CNF is not canonical. Moreover, CNF can be very redundant, so that a large formula is, in fact, equivalent to 0. Looking for a satisfying assignment can be similar to searching for a needle in the hay-stack. The problem may be even harder, if there is no needle there! 18

Example (Deriving CNF) CNF (a + b + c) (a + b + c’) ab cd 00 00 01 11 10 0 1 0 0 0 0 0 (a’ + b + c’) 01 (a + c + d) 11 0 0 0 (a’ + c + d) 10 0 (a’ + c + d’) (b’ + c’ + d’) Cube: bcd’ Clause: b’ + c’ + d (b’ + c’ + d) 19

SAT Solver l SAT solver types l l l CNF-based, circuit-based Complete, incomplete DPLL, saturation, etc. l l l Applications in EDA l Verification l l l l l Equivalence checking Model checking Synthesis Circuit restructuring Decomposition False path analysis Routing A lot of magic is used to build an efficient SAT solver l Two literal clause watching Conflict analysis with clause recording Non-chronological backtracking Variable ordering heuristics Random restarts, etc The best SAT solver is Mini. SAT (http: //minisat. se/) l l Efficient (won many competitions) Simple (600 lines of code) Easy to modify and extend Integrated into ABC 20

Example (SAT Solving) 2 3 (a + b + c) (a + b + ¬c) (¬a + b + ¬c) 4 5 (a + c + d) (¬a + c + d) 6 7 (¬a + c + ¬d) (¬b + ¬c + ¬d) 8 (¬b + ¬c + d) 1 Courtesy Karem Sakallah, University of Michigan a b c d c d d d 21

(2) And-Inverter Graphs (AIG) l l l Definition and examples Several simple tricks that make AIGs work Sequential AIGs Unifying representation A typical synthesis application: AIG rewriting 22

AIG Definition and Examples AIG is a Boolean network composed of two-input ANDs and inverters. a cd b 00 01 11 10 00 0 0 1 1 11 0 10 0 0 1 0 F(a, b, c, d) = ab + d(ac’+bc) a 6 nodes d b 4 levels a a cd b 00 01 11 10 00 0 0 1 1 11 0 10 0 0 1 0 c b c F(a, b, c, d) = ac’(b’d’)’ + c(a’d’)’ = ac’(b+d) + bc(a+d) 7 nodes 3 levels a c b d b c a d 23

Three Simple Tricks l Structural hashing l l Makes sure AIG is always stored in a compact form Is applied during AIG construction l l l d Complemented edges l Represents inverters as attributes on the edges l l Propagates constants Ensures each node is structurally unique c a b Leads to fast, uniform manipulation Does not use memory for inverters Leads to efficient structural hashing Without hashing Memory allocation l Uses fixed amount of memory for each node l l l Can be done by a simple custom memory manager Even dynamic fanout manipulation is supported! Allocates memory for nodes in a topological order l l Optimized for traversal in the same topological order Small static memory footprint for many applications c d a b With hashing 24

Sequential AIGs l Sequential networks have memory elements in addition to logic nodes l l l Several ways of representing sequential AIGs l l l Memory elements are modeled as D-flip-flops Initial state {0, 1, x} is assumed to be given Additional PIs and POs in the combinational AIG Additional register nodes with sequential structural hashing Sequential synthesis (in particular, retiming) annotates registers with additional information l Takes into account register type and its clock domain 25

AIG: A Unifying Representation l An underlying data structure for various computations l l A unifying representation for the whole flow l l l Rewriting, resubstitution, simulation, SAT sweeping, induction, etc are based on the same AIG manager Synthesis, mapping, verification use the same data-structure Allows multiple structures to be stored and used for mapping The main functional representation in ABC l A foundation of new logic synthesis 26

AIG Rewriting l AIG rewriting aims at minimizing the number of AIG nodes without increasing the number of AIG levels Rewriting AIG subgraphs Pre-computing AIG subgraphs Consider function f = abc Subgraph 1 Subgraph 2 a a b a c Rewriting node A a b b b c a A A Subgraph 3 b a c c Subgraph 2 Subgraph 1 c a Rewriting node B B a a b a c b B c Subgraph 2 a b a c Subgraph 1 In both cases 1 node is saved 27

(3) AIG-Based Solutions l Synthesis l Mapping l Verification 28

AIG-Based Solutions (Synthesis) l Restructures AIG or logic network by the following transforms l l Algebraic balancing Rewriting/refactoring/redecomposition Resubstitution Minimization with don't-cares, etc Synthesis D 1 D 2 D 3 D 4 Synthesis with choices D 1 HAIG D 2 D 3 D 4 29

AIG-Based Solutions (Mapping) Input: A Boolean network (And-Inverter Graph) Output: A netlist of K-LUTs implementing AIG and optimizing some cost function f f Technology Mapping a b c d e The subject graph a b c d e The mapped netlist 30

AIG-Based Solutions (Verification) l Property checking l l Takes design and property and makes a miter (AIG) p Equivalence checking l l Property checking 0 D 1 Takes two designs and makes a miter (AIG) The goal is to transform AIG until the output is proved constant 0 Equivalence checking 0 D 1 D 2 31

Summary l Introduced problems in logic synthesis l Representations l Described And-Inverter Graphs (AIGs) l The l and computations foundation of innovative synthesis Overviewed AIG-based solutions l Synthesis, mapping, verification 32