Introduction to HWSW CoSynthesis Algorithms Part of HWSW

Introduction to HW/SW Co-Synthesis Algorithms Part of HW/SW Codesign of Embedded Systems Course (CE 40 -226) 12/05/43 Winter. Spring 2001 Codesign of Embedded Systems 1

Topics n n n Introduction Preliminaries Hardware/Software Partitioning Distributed System Co-Synthesis Conclusions Winter-Spring 2001 Codesign of Embedded Systems 2

Introduction to HW/SW Co-Synthesis Algorithms Introduction 12/05/43 Winter. Spring 2001 Codesign of Embedded Systems 3

Introduction n Implementing a system? Why use CPU? n n n Easier implementation Easier (and cheaper) to change and debug Why use hardware modules? n Meeting other constraints n n performance, power consumption, etc Found a CPU meeting all non-functional constraints? n Yes! What could be better? Use the CPU. No! Design custom logic, or a combination of both n Winter-Spring 2001 Codesign of Embedded Systems 4

Introduction (cont’d) n n Why more than one CPU or custom logic? Why not use the fastest available CPU? Winter-Spring 2001 Codesign of Embedded Systems 5

Introduction (cont’d) n Reason 1: n n Exponential cost per CPU performance Figure: n late-1996 retail prices of Pentium Processor Clock speed (MHz) Pentium processor prices Winter-Spring 2001 Codesign of Embedded Systems 6

Introduction (cont’d) n Exponential price/performance implies n Paying for performance in a uni-processor is very expensive n n Using multiple small CPUs is cheaper Communication overhead is added, but still an economic choice Processors need not be CPUs. But special-function units. Special-purpose PEs can be even cheaper than dedicated CPU! n Winter-Spring 2001 Measured in system manufacturing cost, not necessarily in design cost Codesign of Embedded Systems 7

Introduction (cont’d) n Reason 2: n Scheduling overhead n More than 31% overhead, under reasonable assumptions, when executing multiple processes n n Winter-Spring 2001 Reason: uncertainty in the times at which the processes will need to execute Result: we have to reserve extra CPU horsepower, which comes at exponential cost Codesign of Embedded Systems 8

Introduction (cont’d) n n Still (1997) not quite possible to declare an authoritative taxonomy of co-synthesis models and methods Definition n HW/SW co-synthesis: process of simultaneously design the SW architecture of an application and the HW architecture on which that SW is executed. Winter-Spring 2001 Codesign of Embedded Systems 9

Introduction (cont’d) SW (app. ) Arch. Problem Specification Co. Synthesis Communication Channels HW Engine PE PE PE Winter-Spring 2001 Codesign of Embedded Systems Mem 10

Introduction (cont’d) n Problem specification includes n n Functionality Non-functional requirements n Performance goals, physical constraints, etc Winter-Spring 2001 Codesign of Embedded Systems 11

Introduction (cont’d) n Hardware Architecture n n One or more Processing-Elements (PEs) Software (Application) Architecture includes n Process structure n n n Each process executes sequentially Allocation of the processes onto PEs in the HW engine Communication channels n n Hardware elements Software primitives Winter-Spring 2001 Codesign of Embedded Systems 12

Introduction (cont’d) n HW/SW Co-synthesis n n Allows trade-offs between SW architecutre and HW on which it executes Where is such trade-off important? n n Everyday processing applications vs. Embedded applications Different co-synthesis styles depending on n The Specification The System Components System Elements to synthesize Winter-Spring 2001 Codesign of Embedded Systems 13

Introduction (cont’d) n Two broad implementation styles n HW/SW partitioning n n Target HW architecture: a CPU and multiple ASICs Distributed System Co-synthesis n Target HW architecture: arbitrary hardware topologies Winter-Spring 2001 Codesign of Embedded Systems 14

Introduction to HW/SW Co-Synthesis Algorithms Preliminaries 12/05/43 Winter. Spring 2001 Codesign of Embedded Systems 15

Preliminaries n Rate (execution rate) n n Maximum frequency at which a processing must be done Single-rate vs. Multi-rate n Example of multi-rate system n audio/video decoder Winter-Spring 2001 Codesign of Embedded Systems 16

Preliminaries (cont’d) n Latency n Required maximum time between starting and finishing a processing task Winter-Spring 2001 Codesign of Embedded Systems 17

Preliminaries (cont’d) n Single-rate systems n Standard model: Control-Data Flow Graph (CDFG) n Implies a program-counter or system-state Software n Control-Unit + Data path Not suitable to model multi-rate tasks n unified system state Winter-Spring 2001 Codesign of Embedded Systems 18

Preliminaries (cont’d) n Multi-rate systems n n P 1 Common model: Task Graph P 4 P 5 Task Graph n n n Each Node: Process Each Edge: Communication Each Set of connected nodes: sub-task Winter-Spring 2001 P 2 Codesign of Embedded Systems P 3 P 6 19

What we learned today n n What’s co-synthesis Various keywords used in classification of cosynthesis algorithms Winter-Spring 2001 Codesign of Embedded Systems 20

Complementary notes: Assignments n Take Assignment 9 n Due Date: Wednesday, Khordad 23 th Winter-Spring 2001 Codesign of Embedded Systems 21