Introduction to FPGA Simulation and Debug Objective Understand
Introduction to FPGA Simulation and Debug
Objective • Understand select appropriate debugging tools for FPGA designs. • Hands on use of four different FPGA debug tools • Simulation • Modelsim • Actual Hardware • In-System Sources and Probes • Signal Tap Logic Analyzer • System Console Instrumentation 2
Simulation with Model. Sim
Why Simulation? § + Include wide range of analyses § + Reduce development costs § + Brings innovative products faster to market § + Provide results that are impossible to measure on physical prototype. § + High visibility of all signals in design § - Can take a very long time to run for large designs or excessive stimulus § - Designer has to predict and create stimulus that matches actual behavior 4
Testbenches TESTBENCH A test bench or testing workbench is an environment used to verify the correctness or soundness of a design or model. Design Under Test (DUT) Stimulus Output 5
Verilog Testbench Constructs Timescale Inputs are reg, outputs are wires 1 st number is units, second is timing resolution Note: no module I/O Initial Block Stimulus Runs only once (vs always block) Best to change stimulus on the inactive edge of the clock – easier to read waveforms Use $stop vs $finish or simulator closes Clock 6
Mentor Model. Sim Overview Model. Sim is a multi-language HDL (Verilog/VHDL) simulation environment. It can be used independently or Intel Quartus can create startup scripts and link designs to Model. Sim. § Intel Quartus has a license to distribute Modelsim-Altera with Quartus. § Free Starter Edition: <=10 K lines of code, runs slower 8
Model. Sim Create Project Performed in Quartus Compile Design Note: Only functional (non-timing) simulation is supported Startup Script Back-annotated timing model gate level simulations are not supported Simulate NO OK This script will link in all of external IP libraries so you don’t have to Fix Design YES Done 9
Setting up Model. Sim from Intel Quartus Specify EDA Tool Setting to generate simulation files. § Tools Options EDA Tool Options In Model. Sim-Altera, enter the executable path This path might be different for your own installation! 10
Setting up Model. Sim from Intel Quartus § Assignments Settings EDA Tools Settings Simulation § In Native. Link Settings Test Benches NEW § Add New testbench OK 11
Model. Sim GUI Launching Model. Sim from Quartus Tools Run Simulation Tool RTL Simulation Objects Testbench File Command Transcript Window 12
Lab Exercise 1: MODELSIM
IN-System Sources and probes (issp)
Why ISSP + Quickly set signals to constants: pins or internal nodes + Easily monitor signals – non-triggered continuous display + Works on actual hardware - Not triggered – might miss activity 15
In-System Sources and Probes ISSP allows an easy way to drive and sample signals in hardware and provides a dynamic debugging environment. § ISSP Editor consists of a probe function and interface to control the instances during run time. § It is operated over JTAG. § Each instance can drive and toggle values up to 512 signals. § Can create up to 128 instances of ISSP using IP Catalog 16
What is JTAG - Joint Test Action Group (IEEE JTAG = JTAG is an industry standard for verifying designs and testing printed circuit boards 1149) after manufacture. JTAG implements standards for on-chip instrumentation in electronic design automation as a complementary tool to digital simulation. • FPGAs use this bus as one of the means to configure the device and interface with internal structures in the device Standard 4 or 5 wire bus – used in many digital electronic devices for test and device specific configuration 17
USB Blaster Bridge Circuit Host PC USB This device is commonly a small MAX series nonvolatile device USB to JTAG Bridge JTAG FPGA Development Kit with Integrated USB Blaster 18
In-System Sources and Probes Block Diagram USB 19
Example Uses § Prototype a front panel with virtual buttons for a FPGA Design § Monitor results of changing design constants § Extensive TCL scripting support to create custom automated design control interfaces 20
Using In-System Sources and Probes § Create In-system Sources and Probes IP instances using IP parameter Editor /Mega. Wizard Plug-in Manager (through IP catalog) § Instantiate in design & compile § Program target device 21
IP Parameter Editor for ISSP Instance Index Instance ID # of Sources and Probes Synchronize writing of clks with sources 22
Using In-System Sources and Probes Create and use ISSP Editor (. spf file) to control sources and probes Instance Manager JTAG Chain Configuration p r o b e s Log (Waveform Viewer) Source 23
Signal. Tap Embedded Logic Analyzer
Why Signal Tap + Easily monitor signals – using simple to elaborate triggering schemes + No external equipment required + Don’t need to figure out stimulus since its based on actual hardware - Uses up lots of memory resources inside the chip - Can change timing of design - Requires recompile which takes time 25
Debug of a Design with an External Logic Analyzer Pros: Cons § System-level debug § Signals must be physically accessible on the board by a probe § Can store large quantities of data § Flexible trigger condition § FPGA must have available I/O § If you need a new signal that isn’t accessible, you must make a new board § Probe equipment can potentially effect signal integrity – High quality probes prevents this, but tend to be expensive § Equipment expensive for hobbyist 26
Signal Tap Logic Analyzer Signal. Tap is a logic analyzer made of available resources inside the FPGA § Uses available logic elements to implement the Logic Analyzer § Samples on-chip signals on the rising edge of a specified clock signal § View captured data through the standard JTAG connection typically used for programming the device 27
Debug of a Design with Signal Tap Pros: Cons § Tap signals buried deep in the design § Requires additional device resources (memory and logic elements) – doesn’t change base function, but changes timing § No unassigned I/Os or routing needed § Comes free with all versions of Quartus, no external test equipment required § Must have an active JTAG connection § Tap new signals with the same board by reconfiguring, recompiling, and reprogramming (no re-spin!) 28
What is Signal Tap ?
Create a Signal Tap instance in two ways 1. Use Signal Tap file (. stp) (recommended) § Creates a file (. stp) separate from design files § Convenient features and GUI 2. Use IP Catalog and IP Parameter Editor § Manually instantiate altera_signaltap_ii_logic_analyzer IP core directly into HDL code or Qsys (Platform Designer) § Ties the ELA to the signals directly in RTL 30
Signal Tap Logic Analyzer Window Instance Manager § Identifies which instance is being edited in the GUI § Enable/Disable instances quickly § Gives status and resource utilization (LEs and memory) 31
Signal Tap Logic Analyzer Window JTAG Chain Configuration § Built in “Programmer” § Scans the JTAG chain and identifies available devices 32
Signal Tap Logic Analyzer Window Nodes List § Use the Node Finder to add signals to be tapped § Automatically groups busses together and create custom groups 33
Signal Tap Logic Analyzer Window Trigger Conditions and Qualifiers § Data Enable: Saves signal data (disable to save memory) § Trigger Enable: Signal is part of the trigger condition (disable to save LEs) 34
Signal Tap Logic Analyzer Window Trigger Conditions § Add up to 10 trigger conditions § Choose how every node is compared 35
Signal Tap Logic Analyzer Window Trigger Conditions § Add up to 10 trigger conditions § Choose how every node is compared § Choose what action triggers a specific node 36
Signal Tap Logic Analyzer Window Signal Configuration § Select which clock runs the instance § Sample Depth: how much data from each signal is stored 37
Signal Tap Logic Analyzer Window Signal Configuration § Advanced trigger control § Select the number of trigger conditions § Trigger In/Out options 38
Signal Tap Logic Analyzer Window Data/Setup Window § Setup allows configuration of nodes and trigger conditions (for making edits) § Data shows the acquired signal information (for viewing results) 39
Lab Exercise 2: In-SYSTEM SOURCES AND PROBES Lab Exercise 3: SIGNAL TAP
System Console
Why System Console + Extracts away the complexity of viewing digital waveforms + Super handy for reading and writing memory-mapped elements + Insert and compile once, everything in memory map is settable/viewable + Able to build GUIs to interface with your FPGA - Odd syntax 42
Platform Designer Tool Connect Custom IP and Systems IP 1 Catalog of available IP § Interface Protocols § Memory § DSP § Bridges § PLL § Custom Systems Custom 1 IP 2 Custom 2 Simplify Integration Accelerate Development HDL 43
Platform Designer GUI Parameters IP Catalog System Contents Hierarchy Messages 44
A typical embedded system Master 1 Slave Master 2 Slave We are adding another master to aid in debugging of system components by accessing memory locations of these components. 45
System Console: Easy access to memory space Memory Range Processor (Master 1) 0 x 0000 -0 x 2000 PCI Express (Master 2) 0 x 2001 -0 x 3000 LEDs (Slave 1) 0 x 3001 -0 x 30 F 0 Temperature Sensor (Slave 2) 0 x 30 F 1 -0 x 31 FF On Chip Memory (Slave 3) 0 x 3200 -0 x 5000 Switches (Slave 4) 0 x 3500 -0 x 350 A JTAG to Avalon Memory Master Bridge (Master 3) System Console allows you to see what is in any memory location in a Platform Designer System at any time Add this block to run System Console 0 x 4000 -0 x 5000 46
System Console § Quick System Level debugging of Platform Designer Systems § Interactive TCL console § Debug over various communication channels – JTAG or TCP/IP 48
Usage Examples System-level debug § Board bring-up and interface testing § System clock, reset and JTAG chain validity testing § Qsys component functionality testing § Loopback testing of Avalon Streaming interfaces § Provide test vectors, return responses Other Uses § Debug Transceiver Link § Debug External Memory Interfaces 49
System Console Interfaces System Console Through JTAG and Virtual JTAG Hub Nios II Processor JTAG to Avalon Master Bridge JTAG UART Avalon-ST JTAG Interface Avalon-MM Master Avalon-MM Slave Avalon-ST Source and Sink Interconnect Avalon-MM Slave Avalon-ST Source or Sink User Component 50
System Console GUI Launch 1. Launch System Console from Platform Designer Tools 2. From Nios II Command Shell Type: system-console 51
System Console GUI 52
System Console Services § Collection of functions available to accomplish certain types of tasks § Accessed through a service instance which might be associated with a particular component § Most service instances automatically discovered when System Console starts § Run get_service_types will return all the service types 53
Service Types jtag_debug § JTAG chain debug § Qsys system clock and reset debug device § SOF download bytestream § Access ”character” devices, i. e. jtag_uart master § Provides control of an Avalon master port § Allows reading or writing to any connected Avalon slave 54
Service Types monitor § Efficiently read many Avalon-MM slave memory locations at regular intervals dashboard § Create graphical tools that integrate into the System Console § Use widgets such as buttons, dials, and charts processor § Provides execution control and access to Nios II registers issp § Read from or write to live instances of In-System Sources and Probes modules 55
System Console Usage Flow 1. Add required component to Platform Designer 2. Connect board and program FPGA 3. Launch System Console 4. Locate and open service path 5. Perform desired operation(s) with the service 6. Close the service 56
Components for System Console 1. Add required component to Platform Designer Component Uses Nios II Processor with JTAG Debug Module Debug Avalon-MM slave components Control the Nios II processor to debug functionality JTAG to Avalon Master Bridge Debug components with an Avalon-MM slave interface USB Debug Master Same as JTAG to Avalon Master Bridge but faster Requires USB Blaster II Avalon-ST (Streaming) JTAG Interface Debug components with an Avalon-ST interface JTAG UART Send and receive byte streams Ethernet Components Debugging over TCP/IP (See AN 624) In-System Source and Probes Provides TCL support for ISSP 57
Usage Flow 1. Add required component to Qsys 2. Connect board and program FPGA 3. Launch System Console 4. Locate and open service path 5. Perform desired operation(s) with the service 6. Close the service 58
Locate Service 4. Locate and open service path Locate one of the automatically discovered service instances set m_path [lindex [get_service_paths master] 0] – get_service_paths - returns a list of service instances by type – lindex – Tcl command that retrieves an element from a list – set – Tcl command that sets the value of a variable open_service tells System Console to start using a service instance open_service master $m_path 59
System Console Usage Flow 1. Add required component to Qsys 2. Connect board and program FPGA 3. Launch System Console 4. Locate and open service path 5. Perform desired operation(s) with the service 6. Close the service 60
Perform Desired Operations 5. Perform desired operation(s) with the service Operations depend on service type #Write the data 1 and 2 to address 0 x 2000 master_write_memory $m_path 0 x 2000 [list 0 x 01 0 x 02] #Read two bytes from memory address 0 x 2000 master_read_memory $m_path 0 x 2000 2 61
System Console Usage Flow 1. Add required component to Qsys 2. Connect board and program FPGA 3. Launch System Console 4. Locate and open service path 5. Perform desired operation(s) with the service 6. Close the service 62
Usage Flow – Summary 1. Add required component to Qsys 2. Connect board and program FPGA 3. Launch System Console 4. Locate and open service path 5. Perform desired operation(s) with the service 6. Close the service Complete master write and read example script set m_path [lindex [get_service_paths master] 0] open_service master $m_path master_write_memory $m_path 0 x 2000 [list 0 x 01 0 x 02] master_read_memory $m_path 0 x 2000 2 close_service master $m_path 63
Debug Approach Module level simulation Full chip level simulation Simulation Based Debug Set constant In-chip sources and probes Advanced triggers Signal Tap Instrumentati on with console or GUI System Console Hardware Based Debug 64
Lab Exercise 4: SYSTEM CONSOLE
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