Introduction to Embedded Data Converters Akira Matsuzawa Tokyo

Introduction to Embedded Data Converters Akira Matsuzawa Tokyo Institute of Technology 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 　1

Contents 1. Introduction 2. Characterization of data converters 3. Overview of high-speed A/D converters 4. Overview of high-speed D/A converters 5. Overview of over-sampling sigma-delta data converters 6. Basic design considerations 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 2

1. Introduction • Mixed signal systems – Software defined radio – Digital read channel – Mixed Signal So. C • Progress of ADC and DAC – Power and area – Embedding 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 3

Basic mixed signal system Mixed signal systems basically consist of DSP, ADC, DAC, and pre/post filters. The signals are converted between continuous time and discrete time. Continuous time =Analog AGC Pre Filter Discrete time =Digital ADC DSP Continuous time =Analog DAC Post Filter Clock 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 4

Software defined radio Future wireless systems need powerful ADC and DAC for software defined radio. Future cellular phone needs Multi-standards and multi chips 11 wireless standards!! IMT-2000 RF IMT-2000 BB GSM RF GSM BB Bluetooth RF Bluetooth BB MCU GPS RF GPS BB Power Current Multi-bands and Multi-standards on a single chip Yrjo Neuvo, ISSCC 2004, p. 32 Mixer RF filter Future LNA On a chip PA Filter X Filter ADC Frequency Synthesizer X Filter DSP DAC Mixer 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 5

Mixed signal tech. ; Digital read channel DVD Digital storage needs high speed mixed signal technologies. For the reduction of error rate, high speed ADC is the key. Variable Gain Amp. Analog Filter A to D Converter Digital FIR Filter Viterbi Error Correction Data Out 7 b 400 MHz Data In (Erroneous) Voltage Controlled Oscillator Clock Recovery Pickup signal Analog circuit Digital circuit Data Out (No error) 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 6

Mixed signal So. C can realize full system integration for DVD application. Embedded analog is the key. CPU 2 CPU１ System Controller 0. 13 um, Cu 6 Layer, 24 MTr Pixel Operation Processor Front-End Analog FE +Digital R/C VCO ADC PRML Read Channel Servo DSP Gm-C Filter AV Decode Processor IO Processor Back -End Analog Front End 2006. 14. Okamoto, et al. , ISSCC 2003 VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 7

Progress of high-speed ADC High speed ADC can be embedded in CMOS resulting in power reduction. ISSCC 1991 6 b, 1 GHz ADC 2 W, 1. 5 um Bipolar ISSCC 2000 6 b, 800 MHz ADC 400 m. W, 2 mm 2 0. 25 um. CMOS 10 Pd/ 2 N Gsps [m. W] Matsuzawa, ISSCC 1991 Pd of high speed CMOS ADCs s W 1 m 10 0. 1 World lowest Pd HS ADC 1/8 This Work ps s NG /2 W Sushihara, et al, ISSCC 2000 ISSCC 2002 sp NG /2 1 m 1 10 Conversion rate [x 100 Msps] 7 b, 400 MHz ADC 50 m. W, 0. 3 mm 2 0. 18 um. CMOS Sushihara and Matsuzawa, ISSCC 2002 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 8

Progress of A/D converter; video-rate 10 b ADC 1/2000 in Power and 1/200, 000 in cost during past 20 years ADC was the bottle-neck for the digital TV and Video systems Technology progress has solved this problem. 1980 1982 1993 Now Conventional product World 1 st Monolithic World lowest power So. C Core Board Level (Disc. +Bip) 20 W $ 8, 000 Bipolar (3 um) 2 W $ 800 T. Takemoto and A. Matsuzawa, JSC, pp. 1133 -1138, 1982. 2006. 14. CMOS (1. 2 um) CMOS (0. 15 um) 10 m. W 30 m. W $0. 04 $ 2. 00 K. Kusumoto and A. Matsuzawa, ISSCC 1993. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 9

Power and area reduction of video-rate 10 b ADCs Power and area of ADC have been reducing continuously. Currently, ADC can be embedded on a chip Power reduction 2006. 14. Area reduction VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 10

Power and area reduction of video-rate 10 b ADCs M. Hotta et al. IEICE 2006. June 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 11

Embedding ADC on a CMOS chip CMOS ADC and DAC has been embedded on a CMOS chip. This has realized low cost and low power digital portable AV products. 1993 Model: Portable VCR with digital image stabilizing 6 b Video ADC Digital Video filter A. Matsuzawa, JSC, pp. 470 -480, 1993. System block diagram 8 b low speed ADC; DAC 2006. 14. 8 b CPU VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 12

2. Characterization of data converters • Basic functions of ADC and DAC • Static performance – INL, DNL, monotonicity – Quantization noise • Dynamic performance – – SNR, SFDR, THD, SNDR, ENOB Sampling Jitter ERB Glitch • Figure Of Merit • Performances and applications – Needed performances for wireless systems 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 13

Basic functions of ADC Sampling: Sampling the analog signal with accurate timing. Quantization: Express the converted data with certain accuracy. Quantization Voltage Sampling Time ADC Digital 0001 0010 0111 1000 1001 1000 0111 0101 0010 0100 0111 0110 Coding Quantization Sampling Analog Coding CLK 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 14

Static performance INL and DNL are the major static performance indicators of ADC and DAC. DNL: Differential Non-Linearity INL: Integrated Non-Linearity 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 15

DNL and INL DNL profile 2006. 14. INL profile VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 16

Monotonicity in DAC Binary coded DAC often degrades monotonicity. The monotonicity stands for the qualitative characteristics of data converters of which transfer function keep the monotonic increase or decrease. If the converter can not guarantee the monotonicity, The feedback loop doesn’t work properly and results in backrush. At the change of MSB bit 01111 ->10000 Binary weight 1/32 Out 1/16 1/8 1/2 → 1/4 1/2 Large DNL In In 1/4 1/8 2006. 14. 1/2 1/16 1/32 Keep monotonic VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. Degrade monotonicity 17

Quantization noise Quantization causes noise Higher SNR needs higher resolution Quantization noise Transfer characteristics 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 18

Dynamic performance indicates the ratio between signal and noise or distortion. We should use the suitable terms depending upon the type of application. Fc=40 MHz, fin=4 MHz SFDR=49. 8 d. B SNDR=44. 9 d. B, ENOB=7. 17 -bit 2 nd. HD=-49. 8 d. B, 3 rd. HD=-56. 7 d. B 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 19

Sampling jitter effect Input signal Sampling jitter is converted to noise. When the input frequency becomes higher, the SNR becomes lower. t 2006. 14. t 0 Time VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 20

Effective Resolution Bandwidth ERB is the input frequency where the SNDR has dropped 3 d. B (or ENOB 0. 5 bit) 6 SNR ENOB (bit) 3 d. B (0. 5 bit) down 5 SNDR 4 ERB 3 100 2006. 14. 200 Input frequency (MHz) VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 300 21

Glitch is the spiky signal at code transition. Caused by overlapping of signals This appears within a few psec, However, energy is not negligible. Glitch causes the distortion of signal State 1: [1000]=8 I/2 I/4 I/8 I/16 State 2: [0111]=7 I/2 Glitch I/4 I/8 15 I/16 Current Xg Intermediate: [1111]=15 I/2 2006. 14. I/4 I/8 8 7 Tg I/16 Time VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 22

Figure Of Merit Figure of merit shows energy efficiency for data conversion. 12 b 10 b 1995 -2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 23

Performance and application Needed resolution and conversion rate depending upon the application. Conversion Rate (MHz) 1000 500 300 Graphics HDD/DVD Video/ Communication 100 50 30 10 5 DVC/DSC/Printer Servo Automobile 1 General Purpose 0. 5 (µ-Computer) 0. 1 Audio 0. 05 Meter 6 8 10 12 14 16 Resolution (bits) 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 24

Needed SNR for certain BER in wireless system Lower Bit Error Rate in the digital modulation needs higher SNR. 16 QAM n-PSK Q n-QAM I QPSK 16 QAM 256 QAM 64 QAM Noise distribution “ 0” “ 1” BER 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 25

BER requirement The lower the bit error rate the higher the required ADC/DAC resolution. Resolution (quantization noise) affects BER. DAC requirement for QAM 2006. 14. ADC requirement for digital read-channel VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 26

Signal intensity in wireless system Wireless system has strong unwanted signals. Also, electric circuits generate distortion and noise. Filter A A Intensity (d. B) Filter Far signal C ADC Amp. > Needed dynamic range to the blocker Adjacent signal B C > Needed SNR Wanted signal Due to aliasing Due to distortion of ADC Thermal noise Frequency 2006. 14. B Thermal noise Thermal Noise + Quantization noise VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 27

Needed ADC dynamic range Existence of strong blockers results in the need for high dynamic range ADC. DCS 1800 WCDMA Blocker -26 d. Bm signal Wanted signal ADC dynamic range =86 d. B (14 b) -97 d. Bm 15 d. B Adjacent channel Wanted signal -52 d. Bm -33 d. B Filter attenuation -93 d. Bm Thermal noise Quantization noise 20 d. B 8 d. B -85 d. B ADC dynamic range =36 d. B (6 b) Quantization noise 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 28

3. Overview of high-speed A/D converters • • Performance and ADC architecture Integrating ADC Successive approximation ADC Flash ADC Sub-ranging ADC Interpolation method Folding ADC Pipelined ADC 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 29

ADC performance and architectures There are many conversion architectures with varying performance parameters. Conversion frequency (Hz) 10 G 1 G Flash Pipeline 100 M Sub-range 10 M Multi-bit sigma-delta 1 M 100 k 10 k 4 Successive approximation 6 8 10 Single-bit sigma-delta Integrating 12 14 16 18 20 Resolution (bit) 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 30

Integrating ADC achieves high resolution, but at low speed. Recently it has been used as column-ADC in CMOS imager. -vin S 1 R vref Comparator C PhaseⅠ + vx + PhaseⅡ -vin vref Water clock ・High resolution （20 bit and more） ・Very low speed （DC measurement） ・Small DNL ・Can realize zero offset voltage ・Small analog elements and area Going to 0 -> 1, when Vx becomes negative. vx vin 大 0 T 2006. 14. Time VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 31

Successive-approximation ADC Successive-approximation method is based on a binary search. Vin S/H Comparator b 1 b 2 b 3 VDAC Vref MSB LSB b 1 b 2 b 3 b 4 b 5 b 6 VFS+ VFS VDAC Vin Bout DAC Binary search VFS Balance Successive-approximation resistor and control logic Vin VFS+ VFS CMPin b 1=1 V 0 2006. 14. b 1=1 b 2=0 b 1= b 3= 1 b 1= b 3= b 4= 1 b 2=0 VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 32

Charge-redistribution ADC draws attention as a suitable ADC in the nanometer CMOS era. Because it needs no OP-Amp, but just needs capacitors and comparator. Vx=0 Q=-2 CVin 1) Sampling C C 2 C 4 C 8 C 16 Binary weighted Capacitor array Vin Vref Vx=-Vin Q=-2 CVin 2) Hold C C 2 C 4 C 8 Vin 2006. 14. C 16 Vref VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 33

Charge-redistribution ADC 3) Charge redistribution C 2 C Vx=-Vin+Vref/2 Q=-2 CVin C 4 C 8 C 16 If needed Determine from MSB Vin Vref Higher resolution Easy calibration Ultra low power No OP amp Resistor ladder for higher resolution Low conversion rate Needs multi clock 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 34

Flash ADC is very fast, but area and power increase exponentially with resolution. VDD vin Φ R/2 Ultra fast operation: Several GHz No sample and hold Low resolution: <8 bit Large input capacitance difficult to drive Scale + R R R R/2 2006. 14. Digital out + + Encoder R + 1 10001 Input voltage 01011 + + Comparator 0 D 1 D 2 D 3 D 4 D 5 VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 35

Sub-ranging ADC Multi-step conversion can reduce the # of comparators. However, it needs high precision comparators. As a result, small power and area. Slide gauge Upper conversion 24 Lower conversion 6 4 16 2 0 8 0 GN D 2006. 14. Input voltage VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 36

Interpolation method Interpolation can generate accurate intermediate references which are between two references. Thus step sizes are almost equal, even though mismatch voltages are large. Step size Mismatch voltage Step size Small DNL K. Kusumoto and A. Matsuzawa JSC, pp. 1200 -1206, 1993. 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 37

Folding ADC Input signal is folded to the compressed signals of which phases are different. Lower bits are obtained by comparing between these folded signals. Low power and small size, yet still high speed. However, not suitable for higher resolution. <10 bit vin Folding Circuits Comp Analog signal Digital signal 2006. 14. ① ② ③ Lower bits Logic Folded signals Upper bits ADC Parallel Folded signals ④ Input signal The signal is compressed →The # of comparators can be reduced VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 38

Folding circuits Output voltage Composing the folding characteristics by the summation of currents from differential transistor pairs. VDD V 1 V Input voltage in VDD V 1 V 2 V 3 V 4 Input voltage Current summation Vout Vin VDD vout V 1 V 2 V 3 V 4 V 1 vin 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 39

Pipelined ADC is the centerpiece of embedded ADCs for many applications, such as digital cameras, digital TVs, ADSLs, VDSLs, and wireless LANs. Suitable for CMOS High resolution(<15 bit) Moderate speed(<200 MHz) Low power consumption Switched capacitor operation MSB vin LSB M-bit DAP DAP 2 nd MSB +Vref DAP -Vref +Vref -Vref 0 S/H Digital Approximater (DAP) ADC (M bit) DAC (M bit) + × 2 M +Vref Ｘ２ 0 1 -Vref +Vref Ｘ２ 1 0 1 -Vref Conventional M is 1 or 1. 5 Amplifier 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 40

1. 5 -bit/stage Pipeline ADC Amplification at each stage reduces the input referred thermal noise. 1. 5 b/stage architecture reduces the requirement for the comparator offset drastically. Transfer characteristics +VR S 2 Vi Cf Cs + - LATCH + - SUB-ADC S 3 -VR +VR -VR DAC Vo - MUX +VR + 2 X GAIN Unit conversion stage for 1. 5 -bit/stage pipeline ADC if if if 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 41

Pipelining Pipeline action relaxes settling time requirement. 1 st stage 2 nd Stage 2006. 14. Sample Amp. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 42

4. Overview of high-speed D/A converters • Basic two concepts of DAC • Binary method – R-2 R based DAC – Capacitor array DAC • Decoder method – Resistor string DAC – Current steering DAC 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 43

Basic two concepts of DAC 2. Decoder method Not small DNL Large glitch Small area Small DNL Small glitch Large area Digital 2006. 14. Analog D 3 D 2 D 1 Digital Decoder D 3 D 2 D 1 Binary Weight ckt. Vref 111 110 101 100 011 010 001 000 VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. Vref Switch matrix 1. Binary method Analog 44

Binary method R-2 R based DAC R-2 R resistor ladder can generate binary weighted current easily. Resolution: 12 b Large DNL Small area at high resolution Moderate speed Large power consumption A 0 A 2 A 1 2 R RF A 3 2 R 2 R vout + 2 R Virtual ground -vref R 2006. 14. R R 2 R VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 45

Capacitor array DAC Binary method Capacitor array DAC is widely used in CMOS technology. Low power and no sample & Hold Ai= 0 or 1 16 C Virtual ground Reset 8 C 4 C 2 C + C vout 16 C vref Q Enable 8 C 4 C A 3 2 C A 2 + C A 1 vout A 0 vref 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 46

Decoder method Resistor string DAC Decoder method can realizes small DNL, however needs large area at high resolution. Vref 111 110 101 100 011 010 001 000 Resolution limit: 10 b Good DNL Low speed Small glitch R R R R Vout + large parasitic capacitance: 2 N Digital value R Decoder 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 47

Current steering DAC Decoder method Widely used for high speed DAC. High speed, -- 1 GHz Resolution – 14 b Small DNL Small glitch Graphics, communications, etc. Conventionally large area VDD Vout Di=1 Di Row decoder Di Bias Di=0 Current source Current cell with switch 2006. 14. R Column decoder VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 48

5. Overview of over-sampling sigma-delta data converters • Sigma-delta modulation method – – – – 2006. 14. Over sampling Noise shaping Sigma-delta modulator SNR Higher order system Feed forward and feed back compensation MASH (Multi-stage noise shaping) VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 49

Sigma-delta ADC, DAC Sigma delta ADC and DAC are widely used in high resolution (14 b-24 b) and not high speed ( <1 MHz) applications. Sigma delta ADC Sigma delta DAC Integrator x(n) Comparator + z-1 + Digital Filter 1 bit DAC Analog Digital Signal Processing LPF DAC out C Integrator vin AVDD Φ 1 C Φ 2 Φ 1 + Implemented in CMOS, easily. 1 bit DAC 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 50

Over sampling can reduce effective quantization noise. Band limiting filter x(n) y 1(n) Δ H(f) y 2(n) Quantization noise power he(x) H(f) -fs/2 -fb fb Total noise power is invariant f fs/2 In-band noise Reduction of bandwidth by filter → Reduction of effective noise power 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 51

Noise shaping Spectrum of quantization noise is shaped by differentiator. In-band noise can be reduced. Output signal Integrator 1. 2. Signal intensity Low pass filter 1. Differentiator Quantizer 4. 3. Noise 2. High pass filter 3. Noise BW 4. Noise f Signal: Low pass filter x High pass filter Flat In-band noise is reduced Quantization noise: High pass filter Lower in low frequency The spectrum of the quantization noise increases with frequency increase. Only quantization noise is shaped in frequency characteristics 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 52

Sigma-delta modulator shapes the frequency characteristics of the quantization noise The signal will overflow Integrator Quantizer + X(z) Q(z) Equivalent transform Integrator X(z) + + Differentiator Quantizer Q(z) Differentiator Y(z) + Output Input signal Y(z) Quantization noise Differentiator (High pass filter) No overflow 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 53

Generic expression of sigma-delta modulator We can use not only LPF but also BPF and complex BPF. This gives us an excellent opportunity for wireless applications. Filter Input signal X(z) + H(z) STF (Signal Transfer) Quantizer Output signal Q(z) Y(z) NTF (Noise transfer) Ex. No filter 2006. 14. High pass filter VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 54

Noise power in sigma-delta modulator Lth order filter fb Digital Filter fs=26 MHz 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 55

2 nd order sigma-delta ADC ++ - ++ 1 st order SD ADC -1 z DAC -1 z ++ 1 st order SD ADC - ++ ++ z-1 - DAC ++ Quantizer is replaced by 1 st order SD ADC z-1 z -1 DAC z-1 2 nd order SD ADC ++ - DAC 2006. 14. 1 -1 1 -z ++ - 1 -1 1 -z 2 DAC VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 56

Multi bit sigma-delta ADC ++ - 1 -1 1 -z DAC DAC ++ - 1 -1 1 -z DAC Feedback type ++ - 1 -1 1 -z ++ DAC Feedforward type 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 57

Dynamic range of sigma-delta ADC Higher order SD modulator seems effective to increase the dynamic range. However it is not easy, because of instability, signal saturation, and thermal noise. 5 th 4 th 3 rd n=1 bit 2 nd 1 st OSR 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 58

Noise-shaping characteristics Higher order sigma-delta modulator can realize higher dynamic range, theoretically. 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 59

Cascade (MASH) sigma-delta modulator Cascaded SD modulator can realize higher order noise shaping without stability issues. However, high dynamic range is difficult, due to severe mismatch requirement. ++ - 1 -1 1 -z ++ 2 1 -1 1 -z DAC + ++ - - 1 -1 1 -z + DAC 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 60

6. Basic design considerations • Accuracy – Current mismatch and DAC accuracy – VT mismatch – Capacitor mismatch • Comparator – Offset compensation • Op-Amp – Gain and GBW – k. T/C noise 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 61

Current mismatch and DAC accuracy Larger resolution requires smaller mismatch. INL yield 10% 50% 99. 7% N: resolution C: constant determined by INL yield Van den Bosch, . . Kluwer 2004 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 62

VT mismatch Larger gate area is needed for smaller VT mismatch. Technology scaling reduces VT mismatch if the gate area is equal. 0. 4 um Nch 0. 13 um Nch Boron, w. Halo 0. 13 um Nch In w/o Halo* 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 63

Mismatch current and transistor size Smaller mismatch requires larger L and W. Mismatch 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 64

Capacitor mismatch Smaller capacitor mismatch requires larger capacitance Coefficient depends on the Fab. Typical MIM capacitor 10 bit: 　0. 4 p. F 12 bit: 　４ p. F 14 bit: 40 p. F 10 bit, ¼ LSB 12 bit, ¼ LSB 14 bit, ¼ LSB Capacitance (p. F) 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 65

CMOS comparators There are many types of comparator circuits 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 66

Low power CMOS comparator A CMOS comparator is low power because of no need of static current. No static current Differential comparison Interpolation action High speed CLK T. B. Cho. , et al. , J. S. C. , Vol. 30, No. 30, pp. 166 -172, Mar. 1995. VDD Interpolation action m 11 m 9 m 10 m 12 Out+ Outm 7 m 8 m 5 Vin 1+ m 6 Vin 2+ Vin 1 m 1 m 2 W 1 VSS 2006. 14. Vin 2 m 3 m 4 W 2 W 1 W 2 VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 67

Design rule and Speed in Comparator Gain bandwidth (=Speed) is inversely proportional to the L 2 (channel length). Technology scaling is still effective to increase the comparator speed, if we don’t take care of the signal dynamic range. R R Isink 2006. 14. R R Isink VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 68

Offset compensation Two ways for suppressing offset voltage. Store the offset voltage in capacitors and subtract it from the signal. Feedback= High gain type Vin 1 Vin 2 Va + A - + Vo Latch Vout CLK Vos. A: Offset of the amplifier a) Offset cancel at input nodes Vos. L: Offset of the latch Feed forward =Low gain type Vin 1 Vin 2 + A - + Latch Vout CLK b) Offset cancel at output nodes 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 69

Operational amplifier Higher resolution requires higher open loop gain. Higher conversion frequency requires higher closed loop GBW. Sampling DC gain N: ADC resolution M：Stage resolution Amplify for 1. 5 b pipeline ADC Closed loop gain-bandwidth Equivalent circuit 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 70

k. T/C noise Larger SNR requires larger capacitance and larger signal swing. Low signal swing increases required capacitance. φ n: configuration coefficient vn v out CL VFS=5 V VFS=3 V n=2 14 bit VFS=2 V R SNR (d. B) CL VFS=1 V 12 bit 10 bit 0. 1 1 10 100 Capacitance (p. F) 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 71

Basic design consideration Very tough tradeoffs, so let’s keep up the design effort. Small mismatch Solutions 1) Architecture Pipeline, Parallel 2) Redundancy 3) Error compensation 4) Circuit design Increase Capacitance However, k. T/C issue remains Results in Decrease speed and Increase Power Solutions 1) 2) 2006. 14. Increase signal swing Increase OSR VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 72

Acknowledgement • The author thanks Mr. T. Matsuura from Renesus for some slides provision. 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 73

Study-aid books • B. Razavi, “Data conversion system design, ” IEEE press. • P. E. Allen and D. R. Holberg, “ CMOS Analog Circuit Design, ” 2 nd Edition, OXFORD University Press. • D. A. Johns and K. Martin, “Analog integrated circuit design, ” John Wiley & Sons. • R. J. Baker, “ CMOS mixed-signal circuit design, ” IEEE Press. • R. van de Plassche, “CMOS Integrated Analog-to-Digital and Digital-to -Analog Converters, ” 2 nd Edition, Kluwer Academic Publishers. • M. Gustavsson, J. J. Wikner and N. N. Tan, “CMOS data converters for communications, ” Kluwer Academic Publishers. • C. Shi and M. Ismail, ”Data converters for wireless standards, ” Kluwer Academic Publishers. • A. Rodriguez-Vazquez, F. Mederio, and E. Janssens, “CMOS Telecom Data Converters, ” Kluwer Academic Publishers. 2006. 14. VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 74