Introduction to Digital Systems Multipleoutputs minimization Timing Hazards

Introduction to Digital Systems Multiple-outputs minimization Timing Hazards

Previous… � Po. S minimization � Don’t care values 2

Multiple-Output Minimization � � Most digital applications require multiple outputs derived from the same input variables. Example: 3 inputs and 2 outputs X Y Z � � Logic Circuit F 1 F 2 Each output function could be minimized using K-map and realized independently. The output functions could share one or more product terms (prime implicant) which reduces the total number of gates. 3

Example F 1= XZ+YZ’ u XY X 00 Z 0 1 0 0 01 2 3 11 6 1 7 0 Y u u F 2=XY’+YZ’ 1 1 XY 10 4 5 Z 00 0 1 X Z 1 1 01 2 0 3 0 11 6 1 7 0 10 4 1 5 0 Y XY To find the common terms multiply Z the two functions (F 1. F 2) 0 The common terms are : YZ’, XY’Z 0 1 1 00 0 0 01 2 3 6 7 0 Y Z 1 X 11 1 0 10 4 5 0 1 Z 4

Example - Logic Diagram � Independent realization F 1= XZ+YZ’ F 2= XY’+YZ’ Minimal realization F 1 X Y X Z Y F 2 Z 5

Real-World Logic Design �More than 6 inputs -- can’t use Karnaugh maps �Design correctness more important than gate minimization ◦ Use “higher-level language” to specify logic operations �Use programs to manipulate logic expressions and minimize logic. �PALASM, ABEL, CUPL -- developed for PLDs �VHDL, Verilog -- developed for ASICs 6

Timing Hazards � � � The Truth Table determines the Steady State behavior of a Combinational Logic Circuit Transient behavior: - Output could produce glitches (a short pulse) when input variables change. - Glitches occur when the paths between inputs and output have different delays. - Timing Hazards refer to the possibility of having glitches during input transitions. Hazards : - Definitions. - Finding hazards. - Eliminating hazards. 7

Definitions � � Static Hazards: 1 * Static-1 Hazard : Two input combinations that : 0 - differ in only one variable. - both produce logic 1. - possibly produce Logic 0 glitch during input variable transition * Static-0 Hazard : Two input combinations that 1 - differ in only one variable - Both produce logic 0 0 - Possibly produce Logic 1 glitch during input variable transition Dynamic hazards: - The output could change more than once during input transitions - Caused by multiple paths with different delays from input to the output 8

Example � � � F= YZ+XZ’ Delay in each gate is T. Input changes from XYZ=111 to 110 X Y Z Z’ YZ Y Z F X XZ’ F glitch T 9

Finding Timing hazards using K-map � � Two-level AND-OR Circuits : Static 0 hazards do not exist in the sum-of products (ANDOR) implementation. Static 1 hazards are possible The K-map of the function F in the previous example : - Cell 6 ( 110 ) and cell 7 ( 111 ) are covered in two product terms XY Faster Y 1 Z 1 1 F 0 0 00 Z 0 1 1 0 0 1 1 X 0 1 0 0 01 2 3 11 6 0 7 1 Static 1 hazard Y 1 1 10 4 5 1 0 Z 10

Timing hazards in OR-AND circuits � � � X 0 Z 0 Static 1 hazards do not exist in the Product-of sums (Twolevel OR-AND) implementation. Static 0 hazards are possible The minimal product of F = ( X+Z)(Y+Z’) - Cell 0 ( 000 ) and cell 1 ( 001 ) are covered in two sum terms - Static 0 hazard occurs when inputs switched between 000 to 001 Faster XY X 0 1 F 1 1 0 0 00 Z 1 Y 0 0 0 1 0 0 01 2 3 11 6 0 7 1 Static 0 hazard Y 1 1 10 4 5 1 Z 0 11

Eliminating Timing Hazards � � AND-OR Circuit - Add a prime implicant that combines the two inputs that cause static 1 hazard. ---->consensus - Cells 6 & 7 are combined : XY The hazard-free circuit is : XY 00 Z Y 1 Z 1 X 1 1 0 0 F 0 1 1 0 1 X 0 1 0 0 01 2 3 11 6 1 7 1 10 4 5 1 1 Z 1 Y 12

Eliminating Timing Hazards � � OR-AND Circuit - Add a prime implicant that combines the two inputs that cause static 0 hazard. ---->consensus - Cells 0 & 1 are combined : X+Y The hazard-free circuit is : XY 00 Z X 0 Z 0 0 1 0 F 1 1 Y 0 0 0 X 1 0 0 01 2 3 11 6 0 7 1 10 4 5 1 Z 0 0 Y 13

Summary �A properly designed two-level SOP (AND-OR) circuit has no static-0 hazards. It may have static-1 hazards. � A properly designed two-level POS (OR-AND) circuit has no static-1 hazards. It may have static-0 hazards. � Dynamic hazards do not occur in a properly designed two-level AND-OR or OR-AND circuit. It may occur in multilevel circuits. � A brute-force method of obtaining a hazard-free realization is to use the complete sum or complete product. � Hazard analysis and elimination are typically needed in the design of asynchronous sequential circuits. 14