Introduction to Design Tools COE 1502 Lecture Outline

Introduction to Design Tools COE 1502

Lecture Outline l l Review: Tools, functions, design flow Libraries in FPGA Advantage Setting permissions for group directories Example design: ALU – – – ALU specifications Block diagram editor and embedded blocks Simulation Flow chart editor Component instantiation Truth table editor

Review: Tools, functions, design flow l Four tools we will use in this course – HDL Designer Suite l FPGA Advantage (aka Renoir) – l Model. Sim – l Robust logic simulator Leonardo Spectrum – – IDE to create hierarchical designs and generate HDL Synthesizes HDL into gate-level netlists using device cell libraries Xilinx command-line tools l Place-and-route netlists onto FPGAs

Review: Tools, functions, design flow Generate Compile FPGA Advantage Create symbolic designs VHDL code Proprietary binary format Simulate using Model. Sim EDIF “gate-level” netlist using Xilinx CLBs Xilinx. BIN binary Proprietary text format Synthesize using Leonardo Place-and-route Load onto FPGA and test using LA

Libraries in FPGA Advantage l A library is a collection of components – Components have one or more views (implementations) l – Block diagram, truth table, flow chart, state machine, VHDL architecture Each view has representations: l Graphics, VHDL, simulator netlist, synthesis netlist CPU_lib library component view representation block diagram 1 graphics ALU CPU control_unit block diagram 2 VHDL arch state diagram gen. VHDL sim. binary synth. netlist

Components l Library components can be instantiated in other designs – Shown as green blocks l – Libraries also contain “blocks” l l l – For bottom-up design Attached to the design they were created in Shown as blue blocks For top-down design Embedded blocks – embedded into block diagram l l Shown as yellow blocks Embeds behavior into structure

Libraries in FPGA Advantage l Libraries are stored in four subdirectories in your group directory (e. g. I: alpha) ALU_lib I: alpha CPU_lib – – hds source directory hdl HDL directory work simulation directory ls synthesis directory For each library you use or create, library mappings to these directories must be specified The mappings for your set of libraries are stored in your project file l Lives in your group directory

Setting Permissions on Group Dir. l Right-click your group folder and select “Properties” – Add “Full Control” permissions for yourself and your partner

Projects l l A project in FPGA Advantage is a set of library mappings One partner will create a new project for the group – l l “tutorial” The second partner will open this project Both partners will work within a single project for design of ALU

Projects, Libraries, Components, Views Project Library Component tutorial ALU_Lib ALU Src (hds) HDL Downstream (graphical view) (generated) (compiled for sim) (compiled for synth)

Projects, Libraries, Components, Views Shared Project ieee ALU_Lib src files hdl files CPU COELib sim files CPU_Lib synth files

Example Design: ALU l First partner: Open FPGA Advantage and create your project

Example Design: ALU l Library and project views in Design Manager…

Example Design: ALU

Example Design: ALU l Second group member, open project

Example design: ALU l Specifications for ALU – GOAL: implement all logical, arithmetic, shift, and comparison operations in MIPS instruction set l Operations Bit-wise AND, OR, XOR, and NOR – Signed and unsigned addition, subtraction l Overflow detection, zero-result detection – Signed and unsigned set-on-less-than comparison – Logical shift left and right, arithmetic shift right – – Must accept 2 x 32 -bit operands and produce a 32 -bit result

Example design: ALU l Inputs – – – A, B (32 bits) SHAMT (how many bits? ) ALUOP (how many bits? ) l l 13 total operations Outputs – – – C (32 bits) Overflow Zero

Example design: ALU l We will work top-down to design the ALU – – – First step is to create top-level design Need to choose a view which will implement a VHDL architecture View type: block diagram l – Implements structural VHDL From design browser… l File | New | Graphical View | Block Diagram

Example Design: ALU

Example design: ALU l First, let’s discuss the block diagram toolbars…

Example design: ALU l First, add interface signals with ports (using the toolbar tool, “wire with port”)… l Note signal widths (in wire properties)

Example design: ALU l Save the block diagram into the ALU library – l The component name will be “ALU” Let’s look at the ALU symbol… – – Click “up” in BD, or Use the design browser Source file Symbol file

Example design: ALU l The symbol looks something like this… – We can change the shape and pin locations here l l Right click, then “Autoshapes” Make the symbol look like an ALU symbol

Example design: ALU l Go back to the block diagram window and let’s generate VHDL for our design… l Next, let’s take a look at the VHDL that we generated…

Example design: ALU -- hds header_start --- VHDL Entity ALU. symbol --- Created: -by - jbakos. UNKNOWN (TWEETY) -at - 11: 19: 31 01/07/03 --- Generated by Mentor Graphics' HDL Designer(TM) 2002. 1 a (Build 22) --- hds header_end LIBRARY ieee; USE ieee. std_logic_1164. all; USE ieee. std_logic_arith. all; -- VHDL Architecture ALU. struct --- Created: -by - jbakos. UNKNOWN (TWEETY) -at - 11: 19: 31 01/07/03 --- Generated by Mentor Graphics' HDL Designer(TM) 2002. 1 a (Build 22) -LIBRARY ieee; USE ieee. std_logic_1164. all; USE ieee. std_logic_arith. all; ARCHITECTURE struct OF ALU IS ENTITY ALU IS PORT( A ALUOP B SHAMT C Overflow Zero ); -- Architecture declarations : : : : IN IN OUT OUT -- Declarations END ALU ; -- hds interface_end std_logic_vector std_logic_vector std_logic; std_logic (31 DOWNTO 0); (4 DOWNTO 0); (31 DOWNTO 0); -- Internal signal declarations BEGIN -- Instance port mappings. END struct;

Example design: ALU l Recall that the ALUOp is 4 bits – – l High-order two bits used to determine operation class (ALUOp(3: 2)) Low-order two bits used to determine which operation is performed within each class (ALUOp(1: 0)) Next, let’s define “operation classes” and have subblocks compute intermediate results in parallel… – Logical operations (ALUOp(3: 2) == “ 00”) l – Arithmetic operations (ALUOp(3: 2) == “ 01”) l – SLT, SLTU Shift (ALUOp(3: 2) == “ 11”) l l ADD, ADDU, SUBU Comparison (ALUOp(3: 2) == “ 10”) l – AND, OR, NOR, XOR SLL, SRA Idea: perform each operation type in parallel and select the appropriate output using the two high-order bits of ALUOp

Example design: ALU Use wire tool here l Add subblocks, name them, and wire them up… – Note that ALUOp needs a bus ripper…

Example design: ALU l Let’s take a look at the generated VHDL for the top-level design… – Things to note l l l Same entity statement as before Internal signal declarations Subblocks declared as components (with interfaces) FOR ALL statements Embedded block code Instance port mappings

Example design: ALU LIBRARY ALU; ARCHITECTURE struct OF ALU IS -- Architecture declarations -- Internal signal declarations SIGNAL Arithmetic. R : std_logic_vector(31 SIGNAL Asign : std_logic; SIGNAL Bsign : std_logic; SIGNAL Carry. Out : std_logic; SIGNAL Comparison. R : std_logic_vector(31 SIGNAL Logical. R : std_logic_vector(31 SIGNAL Rsign : std_logic; SIGNAL Shifter. R : std_logic_vector(31 -- Component Declarations COMPONENT Arithmetic PORT ( A : IN std_logic_vector ALUOp : IN std_logic_vector B : IN std_logic_vector Arithmetic. R : OUT std_logic_vector Carry. Out : OUT std_logic ; Overflow : OUT std_logic ; Zero : OUT std_logic ); END COMPONENT; COMPONENT Comparison PORT ( ALUOp : IN std_logic_vector Asign : IN std_logic ; Bsign : IN std_logic ; Carry. Out : IN std_logic ; Rsign : IN std_logic ; Comparison. R : OUT std_logic_vector ); END COMPONENT; DOWNTO 0); (31 DOWNTO 0); (31 DOWNTO 0); (31 DOWNTO 0) COMPONENT Logical PORT ( A : IN ALUOp : IN B : IN Logical. R : OUT ); END COMPONENT; COMPONENT Mux 4 Bus 32 PORT ( ALUOp : IN Arithmetic. R : IN Comparison. R : IN Logical. R : IN Shifter. R : IN R : OUT ); END COMPONENT; COMPONENT Shifter PORT ( A : IN ALUOp : IN SHAMT : IN Shifter. R : OUT ); END COMPONENT; std_logic_vector (31 DOWNTO 0); (31 DOWNTO 0) std_logic_vector std_logic_vector std_logic_vector (3 DOWNTO 2); (31 DOWNTO 0); (31 DOWNTO 0); (1 DOWNTO 0); (4 DOWNTO 0); (31 DOWNTO 0) -- Optional embedded configurations -- pragma synthesis_off FOR ALL : Arithmetic USE ENTITY ALU. Arithmetic; FOR ALL : Comparison USE ENTITY ALU. Comparison; FOR ALL : Logical USE ENTITY ALU. Logical; FOR ALL : Mux 4 Bus 32 USE ENTITY ALU. Mux 4 Bus 32; FOR ALL : Shifter USE ENTITY ALU. Shifter; -- pragma synthesis_on

Example design: ALU BEGIN -- Architecture concurrent statements -- HDL Embedded Text Block 1 eb 1 Asign <= A(31); Bsign <= B(31); Rsign <= Arithmetic. R(31); -- Instance port mappings. I 1 : Arithmetic PORT MAP ( A => A, ALUOp => ALUOp(1 DOWNTO 0), B => B, Arithmetic. R => Arithmetic. R, Carry. Out => Carry. Out, Overflow => Overflow, Zero => Zero ); I 2 : Comparison PORT MAP ( ALUOp => ALUOp(1 DOWNTO 0), Asign => Asign, Bsign => Bsign, Carry. Out => Carry. Out, Rsign => Rsign, Comparison. R => Comparison. R ); I 0 : Logical PORT MAP ( A => ALUOp => B => Logical. R => ); I 4 : Mux 4 Bus 32 PORT MAP ( ALUOp Arithmetic. R Comparison. R Logical. R Shifter. R R ); I 3 : Shifter PORT MAP ( A => ALUOp => SHAMT => Shifter. R => ); END struct; A, ALUOp(1 DOWNTO 0), B, Logical. R => => => ALUOp(3 DOWNTO 2), Arithmetic. R, Comparison. R, Logical. R, Shifter. R, R A, ALUOp(1 DOWNTO 0), SHAMT, Shifter. R

Example design: ALU l Next, let’s create the logical sub-block… – Double-click the logical subblock – This design will perform all four logical operations in parallel and select the desired result using the low-order two bits of ALUOp l l AND => 00 OR => 01 XOR => 10 NOR => 11

Example design: ALU l l l Notice the new block diagram already has the interface ports and signals… Add four embedded blocks (yellow blocks) to implement the operations Next, wire up the blocks to the inputs (A, B), create an output mux, wire it to the output bus and ALUOp We can change the symbols for the yellow blocks We’ll need to assign names for the internal/intermediate signals in the design Add the appropriate concurrent VHDL code for each block – What are concurrent semantics?

Example design: ALU l Let’s take a look at the generated VHDL. . . ARCHITECTURE struct OF Logical IS LIBRARY ieee; USE ieee. std_logic_1164. all; USE ieee. std_logic_arith. all; ENTITY Logical PORT( A ALUOp B Logical. R ); IS : : -- Declarations END Logical ; -- Architecture declarations IN IN IN OUT std_logic_vector (31 DOWNTO 0); (31 DOWNTO 0) -- Internal SIGNAL ANDR SIGNAL NORR SIGNAL XORR signal declarations : std_logic_vector(31 DOWNTO 0); 0); BEGIN -- Architecture concurrent statements -- HDL Embedded Text Block 1 ANDBlock ANDR <= A AND B; -- HDL Embedded Text Block 2 ORBlock ORR <= A OR B; -- HDL Embedded Text Block 3 XORBlock XORR <= A XOR B; -- HDL Embedded Text Block 4 NORBlock NORR <= A NOR B; -- HDL Embedded Text Block 5 Mux 4 B 32 Logical. R <= ANDR when ALUOp="00" else ORR when ALUOp="01" else XORR when ALUOp="10" else NORR; -- Instance port mappings. END struct;

Example design: ALU l Once we’re done, we’ll generate VHDL and compile the design in order to simulate – l The “M” button will perform the entire design flow We’re now presented with the Model. Sim window – – Under the View menu option, open the signals and wave windows Drag the signals from the signals window to the wave window Right click to change radix Structure Drag/drop signals (or right click)

Example design: ALU l From this point, we can use force/run commands to simulate the design – Examples l l l l restart –f view wave add wave /ALU/A force ALUOp “ 0010” force A X” 000000 FF” force A 10#32 run 10 run – l l Turn off warnings Note that the signals can be represented in hexadecimal – l Default runlength is 100 ns Right-click the signals in the wave window to change its properties We can also write a text “. do” file to aid in simulation – Invoked using “do” command l example: – do “i: /alpha/alu/test_logical. do ”

Example design: ALU l l l Let’s go back to the top-level ALU block diagram and create the Shifter subblock We’ll implement the Shifter as a flowchart (useful for testbenches) Flowcharts implement a behavioral VHDL architecture as a process – – – l Primarily, we use: – – – l Processes are executed sequentially, not concurrently Started when signal in sensitivity list changes Allows programming constructs and variables Start/end points Action boxes (also hierarchical) Decision boxes Wait boxes (not synthesizable) Loop boxes Flows Operations are assigned to ALUOp(1: 0) – – – SLL => 00 SRL => 10 SRA => 11

VHDL Process Example ARCHITECTURE REG 4 OF REG 4 a IS BEGIN CLKD : process(D, CLK, EN, RST) begin if(RST = '1') then Q <= "0000"; elsif(CLK'event AND CLK = '0') then if(EN = '1') then Q <= D; end if; end process CLKD; END REG 4;

Example design: ALU l l l Add decision box to check whether this is a left shift or a right shift If this is a left shift, add another decision box to check the least significant bit of SHAMT Then add an action box to assign a variable the input value, shifted 1 bit – l We’ll have to add this variable to the variable declaration list – – – l Note the syntax for assigning variables Under “Flow Chart Properties”, right-click the design We’ll need Left. One, Left. Two, Left. Four, Left. Eight, and Left. Sixteen Right-click, “Flow Chart Properties” Idea: For each set bit n in the SHAMT value, shift the input value 2 n positions to the left – Always shift in 0

Example design: ALU

Example design: ALU

Example design: ALU l For the right shift, there’s a complication – – – What about arithmetic shifts? For this, we use a LOOP block to assign a 16 -bit Fill variable the value we will shift in From then on, we’ll follow the same procedure as with the left shift, but with new variables l l Right. One, Right. Two, Right. Four, Right. Eight, and Right. Sixteen When we’re finished, we’ll simulate this block as we did before

Example design: ALU l Final variable declaration list: variable variable variable Left. One : std_logic_vector(31 downto 0); Left. Two : std_logic_vector(31 downto 0); Left. Four : std_logic_vector(31 downto 0); Left. Eight : std_logic_vector(31 downto 0); Right. One : std_logic_vector(31 downto 0); Right. Two : std_logic_vector(31 downto 0); Right. Four : std_logic_vector(31 downto 0); Right. Eight : std_logic_vector(31 downto 0); Fill : std_logic_vector(31 downto 0);

Example design: ALU

Example design: ALU l Things to consider for the Shifter • What can we use the Shifter for? • How can be divide, say, -13 by 4? • What result should we expect? Why? • Let’s test this in the simulator

Example design: ALU l l l Next, we’ll design the arithmetic subblock as another block diagram We need to implement signed and unsigned addition and subtraction We have a 32 -bit adder component in the COELib library we can instantiate for use in this design Use the green component button to add the ADD 32 component from COELib Wire up the design as follows… ßDrag and drop components from component browser

Modify Downstream Mapping for COELib

Example design: ALU l Let’s note a few things about this design • How does the generated VHDL for the arithmetic block differ from the shifter block? • How is subtraction implemented using an adder? • What is the precise difference between signed and unsigned operations in this context? • How do we detect overflow in signed and unsigned arithmetic? • What reason would we have to detecting a zero result? • How well does our macro file test the unit?

Example design: ALU l Now let’s design the comparison subblock using the truth table view – – Implementing signed and unsigned “set-on-less than” (A < B) We need to utilize the subtraction results from the arithmetic subblock as inputs to the table l Need to make sure the two low-order bits match those for subtraction in the arithmetic unit – – l Outputs from arithmetic unit used as inputs – – l – – – Sign of A Sign of B Output – – The sign of the result Carryout Other inputs we need – – l SLT => 10 SLTU => 11 Single bit output in low-order bit Rows and columns can be added by a right-click Columns can be resized Note: blank cells are considered “don’t cares” Reminder: In VHDL, single bit literals (std_logic) are surrounded by single quotes, bit vectors (std_logic_vector) are surrounded by double quotes

Example design: ALU Initial truth table view – – You will need to add rows You might want to reorder the columns

Example design: ALU l Notes: – – Keep in mind that we’re testing to determine if A is less than B Keep in mind that our inputs assume that the operation being reflected by Rsign and Carry. Out is A - B (SLT) Why do we only consider Rsign when A and B’s signs match? (SLTU) How do we use Carry. Out to perform comparisons?

Example design: ALU Operation A sign B sign R sign Carry. Output SLT + - 0 SLT - + 1 SLT + + + 0 SLT + + - SLT - - + 1 0 SLT - - - 1 SLTU 0 1 SLTU 1 0

Example design: ALU

Example design: ALU -------------------------------------truth_process: PROCESS(ALUOp, Asign, Bsign, Carry. Out, Rsign) -------------------------------------BEGIN -- Block 1 IF (ALUOp(1 DOWNTO 0) = "00") THEN Comparison. R <= "0000000000000000"; ELSIF (ALUOp(1 DOWNTO 0) = "01") THEN Comparison. R <= "00000000000000000000000000000000"; ELSIF (ALUOp(1 DOWNTO 0) = "10") AND (Asign = '0') AND (Bsign = '0') AND (Rsign Comparison. R <= "00000000000000001"; ELSIF (ALUOp(1 DOWNTO 0) = "10") AND (Asign = '1') AND (Bsign = '1') AND (Rsign Comparison. R <= "0000000000000000"; ELSIF (ALUOp(1 DOWNTO 0) = "10") AND (Asign = '1') AND (Bsign = '1') AND (Rsign Comparison. R <= "00000000000000001"; ELSIF (ALUOp(1 DOWNTO 0) = "10") AND (Asign = '0') AND (Bsign = '1') THEN Comparison. R <= "0000000000000000"; ELSIF (ALUOp(1 DOWNTO 0) = "10") AND (Asign = '1') AND (Bsign = '0') THEN Comparison. R <= "00000000000000001"; ELSIF (ALUOp(1 DOWNTO 0) = "11") AND (Carry. Out = '1') THEN Comparison. R <= "0000000000000000"; ELSIF (ALUOp(1 DOWNTO 0) = "11") AND (Carry. Out = '0') THEN Comparison. R <= "00000000000000001"; END IF; END PROCESS truth_process; = '0') THEN = '1') THEN

Example design: ALU l Finally, let’s finish the top-level ALU design by designing the implementation for the Mux 4 bus 32 – For this, we’ll use a VHDL architecture/entity view l Note: the entity is not necessary in this view… it will be generated automatically anyway R <= Logical. R when ALUOp(3 downto 2)="00" else Arithmetic. R when ALUOp(3 downto 2)="01" else Comparison. R when ALUOp(3 downto 2)="10" else Shifter. R;

What is a Testbench? l l “Harness” for a component Interface matching – l Inputs Outputs Allows – – Stimulation of input signals Output signal checking l l l Testbench component – l ASSERTs Waiting/branching based on outputs Block diagram Tester component – Typically a flowchart

Why use Testbenches? l Advantage over ad hoc methods – Ex. do-files l l l Allows simulation of inputs, but no output checking Testbench code reveals interface specification and functionality (“self documenting”) Reproducible – – Can use same testbench for multiple implementations/generations of a component Can generate or utilize data file to share tests between simulation and hardware testing

Test Procedure l A test procedure is a methodology for testing a design – – Sequence of steps Testing aspects of a design’s functionality l Example: ALU Test each type of operation with different inputs – Along with asserting inputs/operations, can also verify correctness of output values – Also, use if-then-else semantics –

Test Procedure l Facilities in FPGA Advantage – – Easy creation of tester/testbench Flowchart view is natural choice for implementing a test bench l – Mirrors test procedure in a graphical representation VHDL support for testbenches l ASSERT/REPORT/SEVERITY clause – l Can use boolean operators here Testbench operates in simulation

Flowchart View • Simple testbench example • Drive inputs • Wait for combinational logic • ASSERT/REPORT/SEVERITY • Repeat