Introduction to CMOS VLSI Design Lecture 6 Logical

Introduction to CMOS VLSI Design Lecture 6: Logical Effort David Harris 6: Logical Effort Harvey Mudd College Spring 2007 1

Outline q q q q RC Delay Estimation Logical Effort Delay in a Logic Gate Multistage Logic Networks Choosing the Best Number of Stages Example Summary 6: Logical Effort CMOS VLSI Design 2

RC Delay Model q Use equivalent circuits for MOS transistors – Ideal switch + capacitance and ON resistance – Unit n. MOS has resistance R, capacitance C – Unit p. MOS has resistance 2 R, capacitance C q Capacitance proportional to width q Resistance inversely proportional to width 6: Logical Effort CMOS VLSI Design 3

RC Values q Capacitance – C = Cg = Cs = Cd = 2 f. F/mm of gate width – Values similar across many processes q Resistance – R 6 KW*mm in 0. 6 um process – Improves with shorter channel lengths q Unit transistors – May refer to minimum contacted device (4/2 l) – Or maybe 1 mm wide device – Doesn’t matter as long as you are consistent 6: Logical Effort CMOS VLSI Design 4

Inverter Delay Estimate q Estimate the delay of a fanout-of-1 inverter 6: Logical Effort CMOS VLSI Design 5

Inverter Delay Estimate q Estimate the delay of a fanout-of-1 inverter 6: Logical Effort CMOS VLSI Design 6

Inverter Delay Estimate q Estimate the delay of a fanout-of-1 inverter 6: Logical Effort CMOS VLSI Design 7

Inverter Delay Estimate q Estimate the delay of a fanout-of-1 inverter d = 6 RC 6: Logical Effort CMOS VLSI Design 8

Example: 3 -input NAND q Sketch a 3 -input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R). 6: Logical Effort CMOS VLSI Design 9

Example: 3 -input NAND q Sketch a 3 -input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R). 6: Logical Effort CMOS VLSI Design 10

Example: 3 -input NAND q Sketch a 3 -input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R). 6: Logical Effort CMOS VLSI Design 11

3 -input NAND Caps q Annotate the 3 -input NAND gate with gate and diffusion capacitance. 6: Logical Effort CMOS VLSI Design 12

3 -input NAND Caps q Annotate the 3 -input NAND gate with gate and diffusion capacitance. 6: Logical Effort CMOS VLSI Design 13

3 -input NAND Caps q Annotate the 3 -input NAND gate with gate and diffusion capacitance. 6: Logical Effort CMOS VLSI Design 14

Elmore Delay q ON transistors look like resistors q Pullup or pulldown network modeled as RC ladder q Elmore delay of RC ladder 6: Logical Effort CMOS VLSI Design 15

Example: 2 -input NAND q Estimate worst-case rising and falling delay of 2 input NAND driving h identical gates. 6: Logical Effort CMOS VLSI Design 16

Example: 2 -input NAND q Estimate rising and falling propagation delays of a 2 input NAND driving h identical gates. 6: Logical Effort CMOS VLSI Design 17

Example: 2 -input NAND q Estimate rising and falling propagation delays of a 2 input NAND driving h identical gates. 6: Logical Effort CMOS VLSI Design 18

Example: 2 -input NAND q Estimate rising and falling propagation delays of a 2 input NAND driving h identical gates. 6: Logical Effort CMOS VLSI Design 19

Example: 2 -input NAND q Estimate rising and falling propagation delays of a 2 input NAND driving h identical gates. 6: Logical Effort CMOS VLSI Design 20

Example: 2 -input NAND q Estimate rising and falling propagation delays of a 2 input NAND driving h identical gates. 6: Logical Effort CMOS VLSI Design 21

Example: 2 -input NAND q Estimate rising and falling propagation delays of a 2 input NAND driving h identical gates. 6: Logical Effort CMOS VLSI Design 22

Delay Components q Delay has two parts – Parasitic delay • 6 or 7 RC • Independent of load – Effort delay • 4 h RC • Proportional to load capacitance 6: Logical Effort CMOS VLSI Design 23

Contamination Delay q Best-case (contamination) delay can be substantially less than propagation delay. q Ex: If both inputs fall simultaneously 6: Logical Effort CMOS VLSI Design 24

Diffusion Capacitance q We assumed contacted diffusion on every s / d. q Good layout minimizes diffusion area q Ex: NAND 3 layout shares one diffusion contact – Reduces output capacitance by 2 C – Merged uncontacted diffusion might help too 6: Logical Effort CMOS VLSI Design 25

Layout Comparison q Which layout is better? 6: Logical Effort CMOS VLSI Design 26

Introduction q Chip designers face a bewildering array of choices – What is the best circuit topology for a function? – How many stages of logic give least delay? – How wide should the transistors be? q Logical effort is a method to make these decisions – Uses a simple model of delay – Allows back-of-the-envelope calculations – Helps make rapid comparisons between alternatives – Emphasizes remarkable symmetries 6: Logical Effort CMOS VLSI Design 27

Example q Ben Bitdiddle is the memory designer for the Motoroil 68 W 86, an embedded automotive processor. Help Ben design the decoder for a register file. q Decoder specifications: – 16 word register file – Each word is 32 bits wide – Each bit presents load of 3 unit-sized transistors – True and complementary address inputs A[3: 0] – Each input may drive 10 unit-sized transistors q Ben needs to decide: – How many stages to use? – How large should each gate be? – How fast can decoder operate? 6: Logical Effort CMOS VLSI Design 28

Delay in a Logic Gate q Express delays in process-independent unit t = 3 RC 12 ps in 180 nm process 40 ps in 0. 6 mm process 6: Logical Effort CMOS VLSI Design 29

Delay in a Logic Gate q Express delays in process-independent unit q Delay has two components 6: Logical Effort CMOS VLSI Design 30

Delay in a Logic Gate q Express delays in process-independent unit q Delay has two components q Effort delay f = gh (a. k. a. stage effort) – Again has two components 6: Logical Effort CMOS VLSI Design 31

Delay in a Logic Gate q Express delays in process-independent unit q Delay has two components q Effort delay f = gh (a. k. a. stage effort) – Again has two components q g: logical effort – Measures relative ability of gate to deliver current – g 1 for inverter 6: Logical Effort CMOS VLSI Design 32

Delay in a Logic Gate q Express delays in process-independent unit q Delay has two components q Effort delay f = gh (a. k. a. stage effort) – Again has two components q h: electrical effort = Cout / Cin – Ratio of output to input capacitance – Sometimes called fanout 6: Logical Effort CMOS VLSI Design 33

Delay in a Logic Gate q Express delays in process-independent unit q Delay has two components q Parasitic delay p – Represents delay of gate driving no load – Set by internal parasitic capacitance 6: Logical Effort CMOS VLSI Design 34

Delay Plots d =f+p = gh + p 6: Logical Effort CMOS VLSI Design 35

Delay Plots d =f+p = gh + p q What about NOR 2? 6: Logical Effort CMOS VLSI Design 36

Computing Logical Effort q DEF: Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current. q Measure from delay vs. fanout plots q Or estimate by counting transistor widths 6: Logical Effort CMOS VLSI Design 37

Catalog of Gates q Logical effort of common gates Gate type Number of inputs 1 2 3 4 n NAND 4/3 5/3 6/3 (n+2)/3 NOR 5/3 7/3 9/3 (2 n+1)/3 2 2 4, 4 6, 12, 6 8, 16, 8 Inverter Tristate / mux XOR, XNOR 6: Logical Effort 1 2 CMOS VLSI Design 38

Catalog of Gates q Parasitic delay of common gates – In multiples of pinv ( 1) Gate type Number of inputs 1 2 3 4 n NAND 2 3 4 n NOR 2 3 4 n 4 6 8 2 n 4 6 8 Inverter Tristate / mux XOR, XNOR 6: Logical Effort 1 2 CMOS VLSI Design 39

Example: Ring Oscillator q Estimate the frequency of an N-stage ring oscillator Logical Effort: Electrical Effort: Parasitic Delay: Stage Delay: Frequency: 6: Logical Effort g= h= p= d= fosc = CMOS VLSI Design 40

Example: Ring Oscillator q Estimate the frequency of an N-stage ring oscillator Logical Effort: Electrical Effort: Parasitic Delay: Stage Delay: Frequency: 6: Logical Effort 31 stage ring oscillator in g=1 0. 6 mm process has h=1 frequency of ~ 200 MHz p=1 d=2 fosc = 1/(2*N*d) = 1/4 N CMOS VLSI Design 41

Example: FO 4 Inverter q Estimate the delay of a fanout-of-4 (FO 4) inverter Logical Effort: Electrical Effort: Parasitic Delay: Stage Delay: 6: Logical Effort g= h= p= d= CMOS VLSI Design 42

Example: FO 4 Inverter q Estimate the delay of a fanout-of-4 (FO 4) inverter Logical Effort: Electrical Effort: Parasitic Delay: Stage Delay: g=1 h=4 p=1 d=5 The FO 4 delay is about 200 ps in 0. 6 mm process 60 ps in a 180 nm process f/3 ns in an f mm process 6: Logical Effort CMOS VLSI Design 43

Multistage Logic Networks q Logical effort generalizes to multistage networks q Path Logical Effort q Path Electrical Effort q Path Effort 6: Logical Effort CMOS VLSI Design 44

Multistage Logic Networks q Logical effort generalizes to multistage networks q Path Logical Effort q Path Electrical Effort q Path Effort q Can we write F = GH? 6: Logical Effort CMOS VLSI Design 45

Paths that Branch q No! Consider paths that branch: G = H = GH = h 1 = h 2 = F = GH? 6: Logical Effort CMOS VLSI Design 46

Paths that Branch q No! Consider paths that branch: G =1 H = 90 / 5 = 18 GH = 18 h 1 = (15 +15) / 5 = 6 h 2 = 90 / 15 = 6 F = g 1 g 2 h 1 h 2 = 36 = 2 GH 6: Logical Effort CMOS VLSI Design 47

Branching Effort q Introduce branching effort – Accounts for branching between stages in path Note: q Now we compute the path effort – F = GBH 6: Logical Effort CMOS VLSI Design 48

Multistage Delays q Path Effort Delay q Path Parasitic Delay q Path Delay 6: Logical Effort CMOS VLSI Design 49

Designing Fast Circuits q Delay is smallest when each stage bears same effort q Thus minimum delay of N stage path is q This is a key result of logical effort – Find fastest possible delay – Doesn’t require calculating gate sizes 6: Logical Effort CMOS VLSI Design 50

Gate Sizes q How wide should the gates be for least delay? q Working backward, apply capacitance transformation to find input capacitance of each gate given load it drives. q Check work by verifying input cap spec is met. 6: Logical Effort CMOS VLSI Design 51

Example: 3 -stage path q Select gate sizes x and y for least delay from A to B 6: Logical Effort CMOS VLSI Design 52

Example: 3 -stage path Logical Effort Electrical Effort H = Branching Effort B = Path Effort Best Stage Effort Parasitic Delay P = Delay D= 6: Logical Effort G= F= CMOS VLSI Design 53

Example: 3 -stage path Logical Effort G = (4/3)*(5/3) = 100/27 Electrical Effort H = 45/8 Branching Effort B = 3 * 2 = 6 Path Effort F = GBH = 125 Best Stage Effort Parasitic Delay P = 2 + 3 + 2 = 7 Delay D = 3*5 + 7 = 22 = 4. 4 FO 4 6: Logical Effort CMOS VLSI Design 54

Example: 3 -stage path q Work backward for sizes y= x= 6: Logical Effort CMOS VLSI Design 55

Example: 3 -stage path q Work backward for sizes y = 45 * (5/3) / 5 = 15 x = (15*2) * (5/3) / 5 = 10 6: Logical Effort CMOS VLSI Design 56

Best Number of Stages q How many stages should a path use? – Minimizing number of stages is not always fastest q Example: drive 64 -bit datapath with unit inverter D = 6: Logical Effort CMOS VLSI Design 57

Best Number of Stages q How many stages should a path use? – Minimizing number of stages is not always fastest q Example: drive 64 -bit datapath with unit inverter D = NF 1/N + P = N(64)1/N + N 6: Logical Effort CMOS VLSI Design 58

Derivation q Consider adding inverters to end of path – How many give least delay? q Define best stage effort 6: Logical Effort CMOS VLSI Design 59

Best Stage Effort q has no closed-form solution q Neglecting parasitics (pinv = 0), we find r = 2. 718 (e) q For pinv = 1, solve numerically for r = 3. 59 6: Logical Effort CMOS VLSI Design 60

Sensitivity Analysis q How sensitive is delay to using exactly the best number of stages? q 2. 4 < r < 6 gives delay within 15% of optimal – We can be sloppy! – I like r = 4 6: Logical Effort CMOS VLSI Design 61

Example, Revisited q Ben Bitdiddle is the memory designer for the Motoroil 68 W 86, an embedded automotive processor. Help Ben design the decoder for a register file. q Decoder specifications: – 16 word register file – Each word is 32 bits wide – Each bit presents load of 3 unit-sized transistors – True and complementary address inputs A[3: 0] – Each input may drive 10 unit-sized transistors q Ben needs to decide: – How many stages to use? – How large should each gate be? – How fast can decoder operate? 6: Logical Effort CMOS VLSI Design 62

Number of Stages q Decoder effort is mainly electrical and branching Electrical Effort: H= Branching Effort: B= q If we neglect logical effort (assume G = 1) Path Effort: F= Number of Stages: 6: Logical Effort N= CMOS VLSI Design 63

Number of Stages q Decoder effort is mainly electrical and branching Electrical Effort: H = (32*3) / 10 = 9. 6 Branching Effort: B=8 q If we neglect logical effort (assume G = 1) Path Effort: F = GBH = 76. 8 Number of Stages: N = log 4 F = 3. 1 q Try a 3 -stage design 6: Logical Effort CMOS VLSI Design 64

Gate Sizes & Delay Logical Effort: Path Effort: Stage Effort: Path Delay: Gate sizes: 6: Logical Effort G= F= z= CMOS VLSI Design y= 65

Gate Sizes & Delay Logical Effort: Path Effort: Stage Effort: Path Delay: Gate sizes: 6: Logical Effort G = 1 * 6/3 * 1 = 2 F = GBH = 154 z = 96*1/5. 36 = 18 CMOS VLSI Design y = 18*2/5. 36 = 6. 7 66

Comparison q Compare many alternatives with a spreadsheet Design N G P D NAND 4 -INV 2 2 5 29. 8 NAND 2 -NOR 2 2 20/9 4 30. 1 INV-NAND 4 -INV 3 2 6 22. 1 NAND 4 -INV-INV 4 2 7 21. 1 NAND 2 -NOR 2 -INV 4 20/9 6 20. 5 NAND 2 -INV-NAND 2 -INV 4 16/9 6 19. 7 INV-NAND 2 -INV 5 16/9 7 20. 4 NAND 2 -INV-INV-INV 6 16/9 8 21. 6 6: Logical Effort CMOS VLSI Design 67

Review of Definitions Term Stage Path number of stages logical effort electrical effort branching effort delay parasitic delay 6: Logical Effort CMOS VLSI Design 68

Method of Logical Effort 1) 2) 3) 4) 5) Compute path effort Estimate best number of stages Sketch path with N stages Estimate least delay Determine best stage effort 6) Find gate sizes 6: Logical Effort CMOS VLSI Design 69

Limits of Logical Effort q Chicken and egg problem – Need path to compute G – But don’t know number of stages without G q Simplistic delay model – Neglects input rise time effects q Interconnect – Iteration required in designs with wire q Maximum speed only – Not minimum area/power for constrained delay 6: Logical Effort CMOS VLSI Design 70

Summary q Logical effort is useful for thinking of delay in circuits – Numeric logical effort characterizes gates – NANDs are faster than NORs in CMOS – Paths are fastest when effort delays are ~4 – Path delay is weakly sensitive to stages, sizes – But using fewer stages doesn’t mean faster paths – Delay of path is about log 4 F FO 4 inverter delays – Inverters and NAND 2 best for driving large caps q Provides language for discussing fast circuits – But requires practice to master 6: Logical Effort CMOS VLSI Design 71