Introduction to CMOS VLSI Design Lecture 2 MIPS

Introduction to CMOS VLSI Design Lecture 2: MIPS Processor Example David Harris 2: MIPS Processor Example Harvey Mudd College Spring 2004 1

Outline q Design Partitioning q MIPS Processor Example – Architecture – Microarchitecture – Logic Design – Circuit Design – Physical Design q Fabrication, Packaging, Testing 2: MIPS Processor Example CMOS VLSI Design 2

Activity 2 q Sketch a stick diagram for a 4 -input NOR gate 2: MIPS Processor Example CMOS VLSI Design 3

Activity 2 q Sketch a stick diagram for a 4 -input NOR gate 2: MIPS Processor Example CMOS VLSI Design 4

Coping with Complexity q How to design System-on-Chip? – Many millions (soon billions!) of transistors – Tens to hundreds of engineers q Structured Design q Design Partitioning 2: MIPS Processor Example CMOS VLSI Design 5

Structured Design q Hierarchy: Divide and Conquer – Recursively system into modules q Regularity – Reuse modules wherever possible – Ex: Standard cell library q Modularity: well-formed interfaces – Allows modules to be treated as black boxes q Locality – Physical and temporal 2: MIPS Processor Example CMOS VLSI Design 6

Design Partitioning q Architecture: User’s perspective, what does it do? – Instruction set, registers – MIPS, x 86, Alpha, PIC, ARM, … q Microarchitecture – Single cycle, multcycle, pipelined, superscalar? q Logic: how are functional blocks constructed – Ripple carry, carry lookahead, carry select adders q Circuit: how are transistors used – Complementary CMOS, pass transistors, domino q Physical: chip layout – Datapaths, memories, random logic 2: MIPS Processor Example CMOS VLSI Design 7

Gajski Y-Chart 2: MIPS Processor Example CMOS VLSI Design 8

MIPS Architecture q Example: subset of MIPS processor architecture – Drawn from Patterson & Hennessy q MIPS is a 32 -bit architecture with 32 registers – Consider 8 -bit subset using 8 -bit datapath – Only implement 8 registers ($0 - $7) – $0 hardwired to 0000 – 8 -bit program counter q You’ll build this processor in the labs – Illustrate the key concepts in VLSI design 2: MIPS Processor Example CMOS VLSI Design 9

Instruction Set 2: MIPS Processor Example CMOS VLSI Design 10

Instruction Encoding q 32 -bit instruction encoding – Requires four cycles to fetch on 8 -bit datapath 2: MIPS Processor Example CMOS VLSI Design 11

Fibonacci (C) f 0 = 1; f-1 = -1 fn = fn-1 + fn-2 f = 1, 1, 2, 3, 5, 8, 13, … 2: MIPS Processor Example CMOS VLSI Design 12

Fibonacci (Assembly) q 1 st statement: n = 8 q How do we translate this to assembly? 2: MIPS Processor Example CMOS VLSI Design 13

Fibonacci (Assembly) 2: MIPS Processor Example CMOS VLSI Design 14

Fibonacci (Binary) q 1 st statement: addi $3, $0, 8 q How do we translate this to machine language? – Hint: use instruction encodings below 2: MIPS Processor Example CMOS VLSI Design 15

Fibonacci (Binary) q Machine language program 2: MIPS Processor Example CMOS VLSI Design 16

MIPS Microarchitecture q Multicycle marchitecture from Patterson & Hennessy 2: MIPS Processor Example CMOS VLSI Design 17

Multicycle Controller 2: MIPS Processor Example CMOS VLSI Design 18

Logic Design q Start at top level – Hierarchically decompose MIPS into units q Top-level interface 2: MIPS Processor Example CMOS VLSI Design 19

Block Diagram 2: MIPS Processor Example CMOS VLSI Design 20

Hierarchical Design 2: MIPS Processor Example CMOS VLSI Design 21

HDLs q Hardware Description Languages – Widely used in logic design – Verilog and VHDL q Describe hardware using code – Document logic functions – Simulate logic before building – Synthesize code into gates and layout • Requires a library of standard cells 2: MIPS Processor Example CMOS VLSI Design 22

Verilog Example module fulladder(input a, b, c, output s, cout); sum s 1(a, b, c, s); carry c 1(a, b, c, cout); endmodule carry(input a, b, c, output cout) assign cout = (a&b) | (a&c) | (b&c); endmodule 2: MIPS Processor Example CMOS VLSI Design 23

Circuit Design q How should logic be implemented? – NANDs and NORs vs. ANDs and ORs? – Fan-in and fan-out? – How wide should transistors be? q These choices affect speed, area, power q Logic synthesis makes these choices for you – Good enough for many applications – Hand-crafted circuits are still better 2: MIPS Processor Example CMOS VLSI Design 24

Example: Carry Logic q assign cout = (a&b) | (a&c) | (b&c); Transistors? Gate Delays? 2: MIPS Processor Example CMOS VLSI Design 25

Example: Carry Logic q assign cout = (a&b) | (a&c) | (b&c); Transistors? Gate Delays? 2: MIPS Processor Example CMOS VLSI Design 26

Example: Carry Logic q assign cout = (a&b) | (a&c) | (b&c); Transistors? Gate Delays? 2: MIPS Processor Example CMOS VLSI Design 27

Gate-level Netlist module carry(input a, b, c, output cout) wire x, y, z; and g 1(x, a, b); and g 2(y, a, c); and g 3(z, b, c); or g 4(cout, x, y, z); endmodule 2: MIPS Processor Example CMOS VLSI Design 28

Transistor-Level Netlist module carry(input a, b, c, output cout) wire i 1, i 2, i 3, i 4, cn; tranif 1 n 1(i 1, 0, a); tranif 1 n 2(i 1, 0, b); tranif 1 n 3(cn, i 1, c); tranif 1 n 4(i 2, 0, b); tranif 1 n 5(cn, i 2, a); tranif 0 p 1(i 3, 1, a); tranif 0 p 2(i 3, 1, b); tranif 0 p 3(cn, i 3, c); tranif 0 p 4(i 4, 1, b); tranif 0 p 5(cn, i 4, a); tranif 1 n 6(cout, 0, cn); tranif 0 p 6(cout, 1, cn); endmodule 2: MIPS Processor Example CMOS VLSI Design 29

SPICE Netlist. SUBCKT CARRY A B C COUT VDD GND MN 1 I 1 A GND NMOS W=1 U L=0. 18 U AD=0. 3 P AS=0. 5 P MN 2 I 1 B GND NMOS W=1 U L=0. 18 U AD=0. 3 P AS=0. 5 P MN 3 CN C I 1 GND NMOS W=1 U L=0. 18 U AD=0. 5 P AS=0. 5 P MN 4 I 2 B GND NMOS W=1 U L=0. 18 U AD=0. 15 P AS=0. 5 P MN 5 CN A I 2 GND NMOS W=1 U L=0. 18 U AD=0. 5 P AS=0. 15 P MP 1 I 3 A VDD PMOS W=2 U L=0. 18 U AD=0. 6 P AS=1 P MP 2 I 3 B VDD PMOS W=2 U L=0. 18 U AD=0. 6 P AS=1 P MP 3 CN C I 3 VDD PMOS W=2 U L=0. 18 U AD=1 P AS=1 P MP 4 I 4 B VDD PMOS W=2 U L=0. 18 U AD=0. 3 P AS=1 P MP 5 CN A I 4 VDD PMOS W=2 U L=0. 18 U AD=1 P AS=0. 3 P MN 6 COUT CN GND NMOS W=2 U L=0. 18 U AD=1 P AS=1 P MP 6 COUT CN VDD PMOS W=4 U L=0. 18 U AD=2 P AS=2 P CI 1 GND 2 FF CI 3 GND 3 FF CA A GND 4 FF CB B GND 4 FF CC C GND 2 FF CCN CN GND 4 FF CCOUT GND 2 FF. ENDS 2: MIPS Processor Example CMOS VLSI Design 30

Physical Design q Floorplan q Standard cells – Place & route q Datapaths – Slice planning q Area estimation 2: MIPS Processor Example CMOS VLSI Design 31

MIPS Floorplan 2: MIPS Processor Example CMOS VLSI Design 32

MIPS Layout 2: MIPS Processor Example CMOS VLSI Design 33

Standard Cells q q q Uniform cell height Uniform well height M 1 VDD and GND rails M 2 Access to I/Os Well / substrate taps Exploits regularity 2: MIPS Processor Example CMOS VLSI Design 34

Synthesized Controller q Synthesize HDL into gate-level netlist q Place & Route using standard cell library 2: MIPS Processor Example CMOS VLSI Design 35

Pitch Matching q Synthesized controller area is mostly wires – Design is smaller if wires run through/over cells – Smaller = faster, lower power as well! q Design snap-together cells for datapaths and arrays – Plan wires into cells – Connect by abutment • Exploits locality • Takes lots of effort 2: MIPS Processor Example CMOS VLSI Design 36

MIPS Datapath q 8 -bit datapath built from 8 bitslices (regularity) q Zipper at top drives control signals to datapath 2: MIPS Processor Example CMOS VLSI Design 37

Slice Plans q Slice plan for bitslice – Cell ordering, dimensions, wiring tracks – Arrange cells for wiring locality 2: MIPS Processor Example CMOS VLSI Design 38

MIPS ALU q Arithmetic / Logic Unit is part of bitslice 2: MIPS Processor Example CMOS VLSI Design 39

Area Estimation q Need area estimates to make floorplan – Compare to another block you already designed – Or estimate from transistor counts – Budget room for large wiring tracks – Your mileage may vary! 2: MIPS Processor Example CMOS VLSI Design 40

Design Verification q Fabrication is slow & expensive – MOSIS 0. 6 mm: $1000, 3 months – State of art: $1 M, 1 month q Debugging chips is very hard – Limited visibility into operation q Prove design is right before building! – Logic simulation – Ckt. simulation / formal verification – Layout vs. schematic comparison – Design & electrical rule checks q Verification is > 50% of effort on most chips! 2: MIPS Processor Example CMOS VLSI Design 41

Fabrication & Packaging q Tapeout final layout q Fabrication – 6, 8, 12” wafers – Optimized for throughput, not latency (10 weeks!) – Cut into individual dice q Packaging – Bond gold wires from die I/O pads to package 2: MIPS Processor Example CMOS VLSI Design 42

Testing q Test that chip operates – Design errors – Manufacturing errors q A single dust particle or wafer defect kills a die – Yields from 90% to < 10% – Depends on die size, maturity of process – Test each part before shipping to customer 2: MIPS Processor Example CMOS VLSI Design 43