Introduction to CMOS VLSI Design Lecture 10 Sequential

Introduction to CMOS VLSI Design Lecture 10: Sequential Circuits David Harris Harvey Mudd College Spring 2004

Outline q q q q Floorplanning Sequencing Element Design Max and Min-Delay Clock Skew Time Borrowing Two-Phase Clocking 10: Sequential Circuits CMOS VLSI Design Slide 2

Sequencing q Combinational logic – output depends on current inputs q Sequential logic – output depends on current and previous inputs – Requires separating previous, current, future – Called state or tokens – Ex: FSM, pipeline 10: Sequential Circuits CMOS VLSI Design Slide 3

Sequencing Cont. q If tokens moved through pipeline at constant speed, no sequencing elements would be necessary q Ex: fiber-optic cable – Light pulses (tokens) are sent down cable – Next pulse sent before first reaches end of cable – No need for hardware to separate pulses – But dispersion sets min time between pulses q This is called wave pipelining in circuits q In most circuits, dispersion is high – Delay fast tokens so they don’t catch slow ones. 10: Sequential Circuits CMOS VLSI Design Slide 4

Sequencing Overhead q Use flip-flops to delay fast tokens so they move through exactly one stage each cycle. q Inevitably adds some delay to the slow tokens q Makes circuit slower than just the logic delay – Called sequencing overhead q Some people call this clocking overhead – But it applies to asynchronous circuits too – Inevitable side effect of maintaining sequence 10: Sequential Circuits CMOS VLSI Design Slide 5

Pipelining 10: Sequential Circuits CMOS VLSI Design Slide 6

Sequencing Methods q Flip-flops q 2 -Phase Latches q Pulsed Latches 10: Sequential Circuits CMOS VLSI Design Slide 7

Timing Diagrams Contamination and Propagation Delays tpd Logic Prop. Delay tcd Logic Cont. Delay tpcq Latch/Flop Clk-Q Prop Delay tccq Latch/Flop Clk-Q Cont. Delay tpdq Latch D-Q Prop Delay tcdq Latch D-Q Cont. Delay tsetup Latch/Flop Setup Time thold Latch/Flop Hold Time 10: Sequential Circuits CMOS VLSI Design Slide 8

Max-Delay: Flip-Flops 10: Sequential Circuits CMOS VLSI Design Slide 9

Max-Delay: Flip-Flops 10: Sequential Circuits CMOS VLSI Design Slide 10

Min-Delay: Flip-Flops 10: Sequential Circuits CMOS VLSI Design Slide 11

Min-Delay: Flip-Flops 10: Sequential Circuits CMOS VLSI Design Slide 12

Positive Skew & Negative Skew PS Clk & Data Same Direction NS Clk & Data Difft Direction 10: Sequential Circuits CMOS VLSI Design Slide 13

Skew: Flip-Flops 10: Sequential Circuits CMOS VLSI Design Slide 14

Skew: Flip-Flops 10: Sequential Circuits CMOS VLSI Design Slide 15

Safe Flip-Flop q In class, use flip-flop with nonoverlapping clocks – Very slow – nonoverlap adds to setup time – But no hold times q In industry, use a better timing analyzer – Add buffers to slow signals if hold time is at risk 10: Sequential Circuits CMOS VLSI Design Slide 16

Summary q Flip-Flops: – Very easy to use, supported by all tools q 2 -Phase Transparent Latches: – Lots of skew tolerance and time borrowing q Pulsed Latches: – Fast, some skew tol & borrow, hold time risk 10: Sequential Circuits CMOS VLSI Design Slide 17