Introduction to CMOS VLSI Design Course Topics q

Introduction to CMOS VLSI Design

Course Topics q Introduction to CMOS circuits q MOS transistor theory, processing technology q CMOS circuit and logic design q System design methods q CAD algorithms for backend design q Case studies, CAD tools, etc. CMOS VLSI Design 2

Bibliography q Textbook – Weste and Harris. CMOS VLSI Design (3 rd edition) • Addison Wesley • ISBN: 0 -321 -14901 -7 • Available at amazon. com. CMOS VLSI Design 3

Introduction q Integrated circuits: many transistors on one chip. q Very Large Scale Integration (VLSI): very many q Complementary Metal Oxide Semiconductor – Fast, cheap, low power transistors q Introduction: How to build your own simple CMOS chip – CMOS transistors – Building logic gates from transistors – Transistor layout and fabrication q Rest of the course: How to build a good CMOS chip CMOS VLSI Design 4

A Brief History q 1958: First integrated circuit – Flip-flop using two transistors – Built by Jack Kilby at Texas Instruments q 2003 – Intel Pentium 4 mprocessor (55 million transistors) – 512 Mbit DRAM (> 0. 5 billion transistors) q 53% compound annual growth rate over 45 years – No other technology has grown so fast so long q Driven by miniaturization of transistors – Smaller is cheaper, faster, lower in power! – Revolutionary effects on society CMOS VLSI Design 5

Annual Sales q 1018 transistors manufactured in 2003 – 100 million for every human on the planet CMOS VLSI Design 6

Invention of the Transistor q Vacuum tubes ruled in first half of 20 th century Large, expensive, power-hungry, unreliable q 1947: first point contact transistor – John Bardeen and Walter Brattain at Bell Labs – Read Crystal Fire by Riordan, Hoddeson CMOS VLSI Design 7

Transistor Types q Bipolar transistors – npn or pnp silicon structure – Small current into very thin base layer controls large currents between emitter and collector – Base currents limit integration density q Metal Oxide Semiconductor Field Effect Transistors – n. MOS and p. MOSFETS – Voltage applied to insulated gate controls current between source and drain – Low power allows very high integration CMOS VLSI Design 8

MOS Integrated Circuits q 1970’s processes usually had only n. MOS transistors – Inexpensive, but consume power while idle Intel 1101 256 -bit SRAM Intel 4004 4 -bit m. Proc q 1980 s-present: CMOS processes for low idle power CMOS VLSI Design 9

Moore’s Law q 1965: Gordon Moore plotted transistor on each chip – Fit straight line on semilog scale – Transistor counts have doubled every 26 months Integration Levels SSI: 10 gates MSI: 1000 gates LSI: 10, 000 gates VLSI: > 10 k gates CMOS VLSI Design 10

CMOS VLSI Design 11

CMOS VLSI Design 12

CMOS VLSI Design 13

Corollaries q Many other factors grow exponentially – Ex: clock frequency, processor performance CMOS VLSI Design 14

Silicon Lattice q Transistors are built on a silicon substrate q Silicon is a Group IV material q Forms crystal lattice with bonds to four neighbors CMOS VLSI Design 15

Dopants q q q Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V: extra electron (n-type) Group III: missing electron, called hole (p-type) CMOS VLSI Design 16

p-n Junctions q A junction between p-type and n-type semiconductor forms a diode. q Current flows only in one direction CMOS VLSI Design 17

n. MOS Transistor q Four terminals: gate, source, drain, body q Gate – oxide – body stack looks like a capacitor – Gate and body are conductors – Si. O 2 (oxide) is a very good insulator – Called metal – oxide – semiconductor (MOS) capacitor – Even though gate is no longer made of metal CMOS VLSI Design 18

n. MOS Operation q Body is commonly tied to ground (0 V) q When the gate is at a low voltage: – P-type body is at low voltage – Source-body and drain-body diodes are OFF – No current flows, transistor is OFF CMOS VLSI Design 19

n. MOS Operation Cont. q When the gate is at a high voltage: – Positive charge on gate of MOS capacitor – Negative charge attracted to body – Inverts a channel under gate to n-type – Now current can flow through n-type silicon from source through channel to drain, transistor is ON CMOS VLSI Design 20

p. MOS Transistor q Similar, but doping and voltages reversed – Body tied to high voltage (VDD) – Gate low: transistor ON – Gate high: transistor OFF – Bubble indicates inverted behavior CMOS VLSI Design 21

Power Supply Voltage q GND = 0 V q In 1980’s, VDD = 5 V q VDD has decreased in modern processes – High VDD would damage modern tiny transistors – Lower VDD saves power q VDD = 3. 3, 2. 5, 1. 8, 1. 5, 1. 2, 1. 0, … CMOS VLSI Design 22

Transistors as Switches q We can view MOS transistors as electrically controlled switches q Voltage at gate controls path from source to drain CMOS VLSI Design 23

CMOS Inverter A Y 0 1 CMOS VLSI Design 24

CMOS Inverter A Y 0 1 0 CMOS VLSI Design 25

CMOS Inverter A Y 0 1 1 0 CMOS VLSI Design 26

CMOS NAND Gate A B 0 0 0 1 1 Y CMOS VLSI Design 27

CMOS NAND Gate A B Y 0 0 1 1 CMOS VLSI Design 28

CMOS NAND Gate A B Y 0 0 1 1 1 0 1 1 CMOS VLSI Design 29

CMOS NAND Gate A B Y 0 0 1 1 1 CMOS VLSI Design 30

CMOS NAND Gate A B Y 0 0 1 1 1 0 CMOS VLSI Design 31

CMOS NOR Gate A B Y 0 0 1 0 1 0 0 1 1 0 CMOS VLSI Design 32

3 -input NAND Gate q Y pulls low if ALL inputs are 1 q Y pulls high if ANY input is 0 CMOS VLSI Design 33

Compound Gates q Compound gates can do any inverting function q Ex: CMOS VLSI Design 34

Example: O 3 AI q CMOS VLSI Design 35

CMOS Fabrication q CMOS transistors are fabricated on silicon wafer q Lithography process similar to printing press q On each step, different materials are deposited or etched q Easiest to understand by viewing both top and crosssection of wafer in a simplified manufacturing process CMOS VLSI Design 36

Inverter Cross-section q Typically use p-type substrate for n. MOS transistors q Requires n-well for body of p. MOS transistors CMOS VLSI Design 37

Well and Substrate Taps q Substrate must be tied to GND and n-well to VDD q Metal to lightly-doped semiconductor forms poor connection (used for Schottky Diode) q Use heavily doped well and substrate contacts / taps CMOS VLSI Design 38

Inverter Mask Set q Transistors and wires are defined by masks q Cross-section taken along dashed line CMOS VLSI Design 39

CMOS VLSI Design 40

Detailed Mask Views q Six masks – n-well – Polysilicon – n+ diffusion – p+ diffusion – Contact – Metal CMOS VLSI Design 41

Fabrication Steps q Start with blank wafer q Build inverter from the bottom up q First step will be to form the n-well – Cover wafer with protective layer of Si. O 2 (oxide) – Remove layer where n-well should be built – Implant or diffuse n dopants into exposed wafer – Strip off Si. O 2 CMOS VLSI Design 42

Oxidation q Grow Si. O 2 on top of Si wafer – 900 – 1200 C with H 2 O or O 2 in oxidation furnace CMOS VLSI Design 43

Photoresist q Spin on photoresist – Photoresist is a light-sensitive organic polymer – Softens where exposed to light CMOS VLSI Design 44

Lithography q Expose photoresist through n-well mask q Strip off exposed photoresist CMOS VLSI Design 45

Etch q Etch oxide with hydrofluoric acid (HF) – Seeps through skin and eats bone; nasty stuff!!! q Only attacks oxide where resist has been exposed CMOS VLSI Design 46

Strip Photoresist q Strip off remaining photoresist – Use mixture of acids called piranha etch q Necessary so resist doesn’t melt in next step CMOS VLSI Design 47

n-well q n-well is formed with diffusion or ion implantation q Diffusion – Place wafer in furnace with arsenic gas – Heat until As atoms diffuse into exposed Si q Ion Implanatation – Blast wafer with beam of As ions – Ions blocked by Si. O 2, only enter exposed Si CMOS VLSI Design 48

Strip Oxide q Strip off the remaining oxide using HF q Back to bare wafer with n-well q Subsequent steps involve similar series of steps CMOS VLSI Design 49

Polysilicon q Deposit very thin layer of gate oxide – < 20 Å (6 -7 atomic layers) q Chemical Vapor Deposition (CVD) of silicon layer – Place wafer in furnace with Silane gas (Si. H 4) – Forms many small crystals called polysilicon – Heavily doped to be good conductor CMOS VLSI Design 50

Polysilicon Patterning q Use same lithography process to pattern polysilicon CMOS VLSI Design 51

N-diffusion q Use oxide and masking to expose where n+ dopants should be diffused or implanted q N-diffusion forms n. MOS source, drain, and n-well contact CMOS VLSI Design 52

N-diffusion (cont. ) q Pattern oxide and form n+ regions CMOS VLSI Design 53

N-diffusion (cont. ) q Historically dopants were diffused q Usually ion implantation today q But regions are still called diffusion CMOS VLSI Design 54

N-diffusion (cont. ) q Strip off oxide to complete patterning step CMOS VLSI Design 55

P-Diffusion q Similar set of steps form p+ diffusion regions for p. MOS source and drain and substrate contact CMOS VLSI Design 56

Contacts q Now we need to wire together the devices q Cover chip with thick field oxide q Etch oxide where contact cuts are needed CMOS VLSI Design 57

Metalization q Sputter on copper / aluminum over whole wafer q Pattern to remove excess metal, leaving wires CMOS VLSI Design 58

Layout q Chips are specified with set of masks q Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) q Feature size f = distance between source and drain – Set by minimum width of polysilicon q Feature size scales ~X 0. 7 every 2 years both lateral and vertical – Moore’s law q Normalize feature size when describing design rules q Express rules in terms of l = f/2 – E. g. l = 0. 3 mm in 0. 6 mm process q Today’s l = 0. 01 mm (10 nanometer = 10 -8 meter) CMOS VLSI Design 59

Simplified Design Rules q Conservative rules to get you started CMOS VLSI Design 60

Inverter Layout q Transistor dimensions specified as Width / Length – Minimum size is 4 l / 2 l, sometimes called 1 unit – In f = 0. 01 mm process, this is 0. 04 mm wide, 0. 02 mm long CMOS VLSI Design 61

Summary q MOS Transistors are stack of gate, oxide, silicon q Can be viewed as electrically controlled switches q Build logic gates out of switches q Draw masks to specify layout of transistors q Now you know everything necessary to start designing schematics and layout for a simple circuit! CMOS VLSI Design 62