Introduction to ABC Alan Mishchenko UC Berkeley Overview

Introduction to ABC Alan Mishchenko UC Berkeley

Overview Introduction l Logic synthesis l l Traditional methods l Recent improvements Formal verification l Conclusions l 2

Introduction l l Design sizes increase Larger logic circuits have to be handled l l Large Boolean expressions arise in other applications l l in both design and verification cryptography, risk analysis, computer-network verification, etc Development of logic synthesis methods continues l l New methods are being discovered (in particular, SAT-based) Scalability of the traditional methods is being improved l Scalability is a “moving target” 3

Logic Synthesis: Definition l l Given a function, derive (synthesize) a circuit Given a poor circuit, improve it Sum of products: Circuit: . i 6. o 1 0 -1 --0 -11 --0 100 -00 1000 -0 --1110 1 1 1 4

Representations of Boolean Functions l l l Truth table (TT) Sum-of-products (SOP) Product-of-sums (POS) Binary decision diagram (BDD) And-inverter graph (AIG) Logic network (LN) F F a b c d a F F = ab+cd b x+cd c ab d F = (a+c)(a+d)(b+c)(b+d) a 0 1 b c d abcd F 0000 0 0001 0 0010 0 0011 1 0100 0 0101 0 0110 0 0111 1 1000 0 1001 0 1010 0 1011 1 1100 1 1101 1 1110 1 1111 1 5

What Representation to Use? l For small functions (up to 16 inputs) l l Truth tables work the best (checking properties, factoring, etc) For medium-sized functions (16 -100 inputs) l l BDDs are still used (reachability analysis) Typically, AIGs work better l l l AIGs can be converted into CNF SAT solver can used for logic manipulation For large industrial circuits (>100 inputs, >10, 000 gates) l l l Flat representations (truth tables, SOPs, BDDs) do not work Traditional logic network representation is not efficient AIGs are a better choice 6

Historical Perspective ABC Problem Size 100000 SIS, VIS, MVSIS 100 Espresso, MIS, SIS 50 AIG 16 TT 1950 -1970 SOP 1980 CNF BDD 1990 2000 2010 Time 7

Traditional Logic Synthesis SOP minimization l Logic network representation l Algebraic factoring l l fast_extract algorithm Don’t-care-based optimization l Technology mapping l 8

SOP Minimization l SOP = Sum-of-Products l l For example: F = ab + cd + abc Given an SOP, minimize the number of products l For example: F = ab + cd + abc = ab + cd l SOP minimization is important because traditional logic synthesis uses SOPs for factoring and node minimization l Tools: l l MINI (IBM, 1974), by S. J. Hong, R. G. Cain, D. L. Ostapko Espresso-MV (IBM / UC Berkeley, 1986) by R. Brayton, R. Rudell 9

Logic Network Representation l In traditional logic synthesis, netlists are represented as DAGs whose nodes can have arbitrary logic functions l l Similar to standard-cell library, with any library gates This representation is general but not well-suited for implementing fast/scalable transformations l Later we will see AIGs are better than logic networks Logic network And-Inverter Graph (AIG) F F = ab+cd F x+cd ab a b c d 10

Algebraic Factoring l l SOP is a two-level (AND-OR) circuit In many applications, a multi-level circuit is needed Algebraic factoring converts SOP into a multi-level circuit Factoring of integers and polynomials is similar l l l 48 = 2 * 2 * 3 a 2 - b 2 = (a + b)*(a - b) The result of factoring of an SOP is not unique l For example: F = ab + ac + bc = a(b+c) + bc = b(a+c) + ac 11

fast_extract Algorithm l l fast_extract (J. Vasudevamurthy and J. Rajski, ICCAD’ 90) is used for algebraic factoring in practice It considers all two-cube divisors and single-cube two-literal divisors and their complement l For example, the 6 -input SOP shown on the right: l l l D 1 = !a + b is a two-cube divisor D 2 = a * !b is a single-cube two-literal divisor D 1 = !D 2 . i 6. o 1 0 -1 --0 -11 --0 100 -00 1000 -0 --1110 1 1 1 It uses a priority queue to find what divisor to extract It updated the SOP and the priority queue after extracting each divisor The resulting factored form is further synthesized by other methods 12

Don’t-Cares l Don’t-cares are input combinations, for which node n in the network can produce any value n y x a a b n b c (x = 0, y = 1) is a satisfiability don’t-care for node n (a = 1, b = 1) is an observability don’t-care for node n 13

Traditional Don’t-Care-Based Optimization l It is a complicated Boolean problem with many variations and improvements – hard to select one “classic algorithm” l l l Compute compatible subsets of observabilty don’t-cares (CODCs) for all nodes in one sweep For each node, project don’t-cares into a local space, and minimize the node’s representation l l Don’t-care represented using BDDs, the node using an SOP The resulting network has smaller local functions l l Below we consider the work of H. Savoj and R. Brayton from early 1990’s Quality of mapping in terms of area and delay are often improved Implementation in SIS (full_simplify) has not been widely used l Slow and unscalable in many cases 14

Example of Using Don’t-Cares Original function: F = ab + d(a!c+bc) Complete don’t-cares: F=b 00 01 11 10 00 0 - - 0 1 01 0 - 1 1 0 10 0 - 00 01 11 10 00 0 0 1 11 0 1 10 0 0 Optimized function: 00 01 11 10 00 0 1 1 0 - 01 0 1 0 10 0 1 1 0 15

Technology Mapping Input: A Boolean network (And-Inverter Graph) Output: A netlist of K-LUTs implementing AIG and optimizing some cost function f f Technology Mapping a b c d e The subject graph a b c d e The mapped netlist 16

Recent Improvements AIG: standard logic representation l Synthesis l l Improved factoring l Improved (SAT-based) don’t-care computation l Using structural choices Mapping l Verification l 17

And-Inverter Graph (AIG) Definition and Examples AIG is a Boolean network composed of two-input ANDs and inverters a cd b 00 01 11 10 00 0 0 1 1 11 0 10 0 0 1 0 F(a, b, c, d) = ab + d(a!c+bc) 6 nodes a 4 levels d b a a cd b 00 01 11 10 c b c F(a, b, c, d) = a!c(b+d) + bc(a+d) 00 0 0 1 1 7 nodes 11 0 1 1 0 3 levels 10 0 0 1 0 a c b d b c a d 18

Components of Efficient AIG Package l Structural hashing l l Leads to a compact representation Is applied during AIG construction l l l d Complemented edges l Represents inverters as attributes on the edges l l Propagates constants Makes each node structurally unique c a b Leads to fast, uniform manipulation Does not use memory for inverters Increases logic sharing using De. Morgan’s rule Without hashing Memory allocation l Uses fixed amount of memory for each node l l l Allocates memory for nodes in a topological order l l l Can be done by a custom memory manager Even dynamic fanout can be implemented this way Optimized for traversal using this topological order Small static memory footprint for many applications Computes fanout information on demand c d a b With hashing 19

AIG: A Unifying Representation l An underlying data structure for various computations l l A unifying representation for the computation flow l l l Rewriting, resubstitution, simulation, SAT sweeping, etc, are based on the AIG manager Synthesis, mapping, verification use the same data-structure Allows multiple structures to be stored and used for mapping The main circuit representation in our software (ABC) 20

Improved Algebraic Factoring l l l Traditional factoring finds divisors by enumerating cube pairs (quadratic in the number of cubes) Recent improvement (B. Schmitt, ASP-DAC’ 17) computes the same divisors using a hash table The new implementation is linear in the number of cubes and scales better in practice l Compare commands “fx” and “fxch” in ABC 21

SAT-based Methods l Currently many hard computational problems are formulated and solved using Boolean satisfiability l l Heuristic solutions are often based on exact minimum results computed for small problem instances l l Resubstitution, decomposition, delay/area optimization, etc (and also technology mapping, detailed placement, routing, etc) For example, technology mapping for a small multi-output subject graph (20 -30 nodes) is solved exactly in a short time A larger design is optimized by a sliding window approach A robust formulation is as important as a fast SAT solver Don’t-cares can be efficiently used during synthesis without computing them 22

Terminology l Logic function (e. g. F = ab+cd) l l l Variables (e. g. b) Literals (e. g. b and !b) Minterms (e. g. a!bcd) Cubes (e. g. ab) Logic network l l l Primary inputs/outputs Logic nodes Fanins/fanouts Transitive fanin/fanout cone Cuts and windows Primary outputs TFO Fanouts Fanins TFI Primary inputs 23

Don’t-Care-Based Optimization l Definition l l A window for node n in the network is the context, in which its functionality is considered A window includes l l l k levels of the TFI m levels of the TFO all re-convergent paths contained in this scope Window POs m=3 n k=3 Window PIs 24

Characterizing Don’t-Cares Construction steps l l l Divisors are not in the TFO of n Their support is a subset of that of node n Duplicate the window of node n l l 1 Collect candidate divisors di of node n Use the same set of input variables Use a different set of output variables … Add inverter for node n in one copy Create comparator for the outputs Set the comparator to 1 l This is the care set of node n Use in SAT-based synthesis l l l Convert the circuit to CNF Add this CNF to the SAT solver as a constraint to characterize don’t-cares without computing them explicitly SAT solver is used to derive different functions F(d 1, d 2, …) implementing node n in terms of divisors d 1, d 2, … d 1 n d 2 n 25 X

Synthesis with Choices l l Traditional synthesis explores a sequence of netlist snapshots Modern synthesis allows for snapshots to be mixed-and-matched l This is achieved by computing structural choices Traditional synthesis D 1 D 2 D 3 D 4 Synthesis with structural choices D 1 HAIG D 2 D 4 D 3 26

Choice Computation l Input is several versions of the same netlist l l For example, area- and delay-optimized versions Output is netlist with “choice nodes” l Fanins of a choice node are functionally equivalent and can be used interchangeably l Structural choices are given to a technology mapper, which uses them to mix-and-match different structures, resulting in improved area/delay l Computation l l Combine netlists into one netlist (share inputs, append outputs) Detect all pairs of equivalent nodes in the netlist (SAT sweeping) Record node pairs proved functionally equivalent by the SAT solver Re-hash the netlist with these equivalences and create choice nodes 27

Modern Technology Mapping l Unification of all types of mappers l l Standard cells, LUTs, programmable cells, etc Using structural choices in all mappers State-of-the-art heuristics use two good cuts at a node Several flavors of SAT-based mapping are researched l l l Currently SAT is limited to post-processing/optimization Also, SAT is used to pre-compute optimal results for small functions May appear in the main-stream mappers in the future 28

Summary of “Modern Synthesis” l l l Using AIGs to represent circuits in all computations Using simulation and SAT for Boolean manipulation Achieving (near-) linear complexity in most algorithms by performing iterative local computations l l Often using pre-computed data, hashing, truth tables, etc Scaling to 10 M+ AIG nodes in many computations 29

Formal Verification l Goal l l Formal vs. “informal” l l l l Dealing with real designs Modeling sequential logic (initialization, clock domains, etc) Modeling the environment (need support for constraints) Dealing with very large problems (need robust abstraction) Industrial adoption is hindered by lack of understanding how to apply formal and by weakness of the tools Two aspects of formal l Simulation is often not enough Bounded verification is important but often not enough Difficulties l l Making sure the design performs according to the spec Front-end (modeling) Back-end (solving) In this presentation, we are mostly talking about the backend 30

Sequential Miter l l l A sequential logic circuit The result of modeling by frontend To be solved by backend Equivalence checking l Equivalence checking Miter contains two copies of the design (golden and implementation) 0 D 2 D 1 Model checking l Miter contains one copy of the design and a property to be verified The goal is to transform the miter presented as a sequential AIG, and prove that the output is constant 0 Property checking p 0 D 1 31

Outcomes of Verifying a Property l Success l l Failure l l The property holds in all reachable states A finite-length counter-example (CEX) is found Undecided l A limit on resources (such as runtime) is reached 32

Certifying Verification l How do we know that the answer produced by a verification tool is correct? l l If the result is “SAT”, re-run the resulting CEX to make sure that it is valid If the result is “UNSAT”, an inductive invariant can be generated and checked by a third-party tool 33

Inductive Invariant l An inductive invariant is a Boolean function in terms of register variables, such that l l It is true for the initial state(s) It is inductive l l assuming that it holds in one (or more) time-frames allows us to prove it in the next time-frame State space Bad Invariant Reached Init It does not contain “bad states” where property fails 34

Verification Engines l Provers l l l Bug-hunters l l K-step induction, with or without uniqueness constraints BDDs (exact reachability) Interpolation (over-approximate reachability) Property directed reachability (over-approximate reachability) Interval property checking Random simulation Bounded model checking (BMC) Hybrids of the two (“semi-formal”) Transformers l l l Combinational optimization Retiming etc 35

Integrated Verification Flow Creating sequential miter Initial simplification Progressive solving Last-gasp solving l Deriving logic for gates or RTL Modeling clocks, multi-phase clocking Representing initialization logic, etc l Structural hashing, sequential cleanup, etc l Applying engine sequences (concurrently) Using abstraction, speculation, etc l l Trying to prove or find a bug with high resource limits 36

ABC in Design Flow System Specification RTL Logic synthesis Technology mapping Verification ABC Physical synthesis Manufacturing 37

Summary Introduced logic synthesis l Described representations and algorithms l Outlined recent improvements l 38

ABC Resources l Tutorial l Complete source code l l R. Brayton and A. Mishchenko, "ABC: An academic industrialstrength verification tool", Proc. CAV'10, LNCS 6174, pp. 24 -40. http: //www. eecs. berkeley. edu/~alanmi/publications/2010/cav 10_ abc. pdf https: //bitbucket. org/alanmi/abc Windows binary l l http: //www. eecs. berkeley. edu/~alanmi/abc. exe http: //www. eecs. berkeley. edu/~alanmi/abc. rc 39

Abstract l This talk will review the development of logic synthesis from manipulating small Boolean functions using truth tables, through the discovery of efficient heuristic methods for sum-of-product minimization and algebraic factoring applicable to medium-sized circuits, to the present-day automated design flow, which can process digital designs with millions of logic gates. The talk will discuss the main computation engines and packages used in logic synthesis, such as circuit representation in the form of And-Inverter-Graphs, recent improvements to the traditional minimization and factoring methods, priority-cut-based technology mapping into standard-cells and lookuptables, and don't-care-based optimization using Boolean satisfiability. We will also discuss the importance of formal verification for validating the results produced by the synthesis tools, and the deep synergy between algorithms and data-structures used in synthesis and verification. In the course of this talk, the presenter will share his 14 -year experience of being part of an academic research group with close connections to companies in Silicon Valley, both design houses and CAD tool vendors. 40

Bio l Alan Mishchenko graduated from Moscow Institute of Physics and Technology, Moscow, Russia, in 1993. Alan received his Ph. D. from Glushkov Institute of Cybernetics, Kiev, Ukraine, in 1997. In 2002, Alan started at University of California at Berkeley as an Assistant Researcher and, in 2013, he became a Full Researcher. Alan shared the D. O. Pederson TCAD Best Paper Award in 2008 and the SRC Technical Excellence Award in 2011 for work on ABC. His research interests are in developing efficient methods for logic synthesis and verification. 41