Introduction Datapath Basics 1 CPU performance factors Instruction

Introduction Datapath Basics 1 CPU performance factors - Instruction count; determined by ISA and compiler CPI and Cycle time; determined by CPU hardware We will examine a simplified MIPS implementation in this course and a more realistic pipelined version in the next. Simple subset of machine instructions, shows most aspects - CS@VT August 2009 Memory reference: lw, sw Arithmetic/logical: add, sub, and, or, slt Control transfer: beq, j Computer Organization I © 2006 -09 Mc. Quain, Feng & Ribbens

Review of MIPS Machine Language Datapath Basics 2 Simple instructions, all 32 bits wide Very structured, no unnecessary baggage Only three instruction formats: R op rs rt rd I op rs rt 16 -bit immediate J op shamt funct 26 -bit immediate Basic arithmetical-logical instructions are R-format. Load/store/conditional branch instructions are I-format. Jump/unconditional branch instructions are J-format. CS@VT August 2009 Computer Organization I Mc. Quain Ribbens © 2006 -09 © 2009 Mc. Quain, Feng && Ribbens

Instruction Execution Datapath Basics 3 PC instruction memory, fetch instruction Register numbers register file, read registers Depending on instruction class - Use ALU to calculate - - CS@VT August 2009 Arithmetic result Memory address for load/store Branch target address Access data memory for load/store PC target address or PC + 4 Computer Organization I © 2006 -09 Mc. Quain, Feng & Ribbens

CPU Overview CS@VT August 2009 Datapath Basics 4 Computer Organization I © 2006 -09

Need for Selection Mechanisms Must choose which one goes back to PC. Compute address for sequential execution. CS@VT August 2009 Datapath Basics 5 BUT, you cannot just join wires together to achieve this… Compute address for conditional branch. Computer Organization I © 2006 -09 Mc. Quain, Feng & Ribbens

Need for Control Logic The 2 x 1 multiplexor must have a 1 -bit control line to select between the two inputs. Datapath Basics 6 There must be a combinational circuit that determines which input should be selected and passed through to the PC. So, under what condition(s) should the branch address be used? … if we're executing a conditional branch instruction and the condition has evaluated to true. CS@VT August 2009 Computer Organization I © 2006 -09 Mc. Quain, Feng & Ribbens

Control Questions Datapath Basics 7 What's the logic for controlling the other MUXes? What goes here? CS@VT August 2009 What control settings will the ALU need? Computer Organization I © 2006 -09 Mc. Quain, Feng & Ribbens

Logic Design Basics Datapath Basics 8 Information encoded in binary - Low voltage = 0, High voltage = 1 One wire per bit Multi-bit data encoded on multi-wire buses Combinational elements - Operate on data Output is purely a function of input State (sequential) elements - CS@VT August 2009 Store information Output/state depends on input and on previous state Computer Organization I © 2006 -09 Mc. Quain, Feng & Ribbens

Clocking Methodology Datapath Basics 9 Combinational logic transforms data during clock cycles - CS@VT August 2009 Between clock edges Input from state elements, output to state element Longest delay determines clock period Computer Organization I © 2006 -09 Mc. Quain, Feng & Ribbens

Building a Datapath Basics 10 Datapath - Elements that process data and addresses in the CPU Registers, ALUs, mux’s, memories, … We will build a MIPS datapath incrementally - CS@VT August 2009 Refining the overview design Computer Organization I © 2006 -09 Mc. Quain, Feng & Ribbens

Instruction Fetch Datapath Basics 11 Increment by 4 for next instruction 32 -bit register

R-Format Instructions Datapath Basics 12 Read two register operands Perform arithmetic/logical operation Write register result op CS@VT August 2009 rs rt rd Computer Organization I shamt funct © 2006 -09 Mc. Quain, Feng & Ribbens

Load/Store Instructions Datapath Basics 13 Read register operands Calculate address using 16 -bit offset - Use ALU, but sign-extend offset Load: Read memory and update register Store: Write register value to memory op CS@VT August 2009 rs rt 16 -bit immediate Computer Organization I © 2006 -09 Mc. Quain, Feng & Ribbens

Branch Instructions Datapath Basics 14 Read register operands Compare operands - Use ALU, subtract and check Zero output Calculate target address - Sign-extend displacement Shift left 2 places (word displacement) Add to PC + 4 - Already calculated by instruction fetch op CS@VT August 2009 rs rt 16 -bit immediate Computer Organization I © 2006 -09 Mc. Quain, Feng & Ribbens