Introduction COE 301 Computer Organization Prof Aiman ElMaleh

Introduction COE 301 Computer Organization Prof. Aiman El-Maleh College of Computer Sciences and Engineering King Fahd University of Petroleum and Minerals [Adapted from slides of Dr. M. Mudawar, COE 301, KFUPM]

Next. . . v High-Level, Assembly-, and Machine-Languages v Components of a Computer System v Technology Improvements v Programmer’s View of a Computer System Introduction COE 301– KFUPM slide 2

Some Important Questions to Ask v What is Assembly Language? v What is Machine Language? v How is Assembly related to a high-level language? v Why Learn Assembly Language? v What is an Assembler, Linker, and Debugger? Introduction COE 301– KFUPM slide 3

A Hierarchy of Languages Application Programs High-Level Languages Machine independent High-Level Language Machine specific Low-Level Language Assembly Language Machine Language Hardware Introduction COE 301– KFUPM slide 4

Assembly and Machine Language v Machine language ² Native to a processor: executed directly by hardware ² Instructions consist of binary code: 1 s and 0 s v Assembly language ² Slightly higher-level language ² Readability of instructions is better than machine language ² One-to-one correspondence with machine language instructions v Assemblers translate assembly to machine code v Compilers translate high-level programs to machine code ² Either directly, or ² Indirectly via an assembler Introduction COE 301– KFUPM slide 5

Compiler and Assembler Introduction COE 301– KFUPM slide 6

Instructions and Machine Language v Each command of a program is called an instruction (it instructs the computer what to do). v Computers only deal with binary data, hence the instructions must be in binary format (0 s and 1 s). v The set of all instructions (in binary form) makes up the computer's machine language. This is also referred to as the instruction set. Introduction COE 301– KFUPM slide 7

Instruction Fields v Machine language instructions usually are made up of several fields. Each field specifies different information for the computer. The major two fields are: v Opcode field which stands for operation code and it specifies the particular operation that is to be performed. ² Each operation has its unique opcode. v Operands fields which specify where to get the source and destination operands for the operation specified by the opcode. ² The source/destination of operands can be a constant, the memory or one of the general-purpose registers. Introduction COE 301– KFUPM slide 8

Translating Languages Program (C Language): A statement in a high-level language is translated typically into several machine-level instructions swap(int v[], int k) { int temp; temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; } Compiler MIPS Machine Language: MIPS Assembly Language: sll add lw lw sw sw jr $2, $5, 2 $2, $4, $2 $15, 0($2) $16, 4($2) $16, 0($2) $15, 4($2) $31 Introduction Assembler COE 301– KFUPM 00051080 00821020 8 C 620000 8 CF 20004 ACF 20000 AC 620004 03 E 00008 slide 9

Advantages of High-Level Languages v Program development is faster ² High-level statements: fewer instructions to code v Program maintenance is easier ² For the same above reasons v Programs are portable ² Contain few machine-dependent details § Can be used with little or no modifications on different machines ² Compiler translates to the target machine language ² However, Assembly language programs are not portable Introduction COE 301– KFUPM slide 10

Why Learn Assembly Language? v Many reasons: ² Accessibility to system hardware ² Space and time efficiency v Accessibility to system hardware ² Assembly Language is useful for implementing system software ² Also useful for small embedded system applications v Space and Time efficiency ² Understanding sources of program inefficiency ² Tuning program performance ² Writing compact code Introduction COE 301– KFUPM slide 11

Assembly Language Programming Tools v Editor ² Allows you to create and edit assembly language source files v Assembler ² Converts assembly language programs into object files ² Object files contain the machine instructions v Linker ² Combines object files created by the assembler with link libraries ² Produces a single executable program v Debugger ² Allows you to trace the execution of a program ² Allows you to view machine instructions, memory, and registers Introduction COE 301– KFUPM slide 12

Assemble and Link Process Source File Assembler Object File Linker Assembler Object File Link Libraries Source File Executable File A project may consist of multiple source files Assembler translates each source file separately into an object file Linker links all object files together with link libraries Introduction COE 301– KFUPM slide 13

MARS Assembler and Simulator Tool Introduction COE 301– KFUPM slide 14

MARS Assembler and Simulator Tool v Simulates the execution of a MIPS program ² No direct execution on the underlying Intel processor v Editor with color-coded assembly syntax v Assembler Converts MIPS assembly language programs into object files v Debugger ² Allows you to trace the execution of a program and set breakpoints ² Allows you to view machine instructions, edit registers and memory Introduction COE 301– KFUPM slide 15

Next. . . v High-Level, Assembly-, and Machine-Languages v Components of a Computer System v Technology Improvements v Programmer’s View of a Computer System Introduction COE 301– KFUPM slide 16

Components of a Computer System v Processor Computer ² Datapath Memory ² Control I/O Devices v Memory & Storage ² Main Memory ² Disk Storage Input Control Processor B U S Datapath v Input devices v Output devices Output Disk Network v Bus: Interconnects processor to memory and I/O v Network: newly added component for communication Introduction COE 301– KFUPM slide 17

Memory v Ordered sequence of bytes ² The sequence number is called the memory address v Byte addressable memory ² Each byte has a unique address ² Supported by almost all processors v Physical address space ² Determined by the address bus width ² Pentium has a 32 -bit address bus § Physical address space = 4 GB = 232 bytes ² Itanium with a 64 -bit address bus can support § Up to 264 bytes of physical address space Introduction COE 301– KFUPM slide 18

Address Space is the set of memory locations (bytes) that can be addressed Introduction COE 301– KFUPM slide 19

Address, Data, and Control Bus v Address Bus ² Memory address is put on address bus ² If memory address = a bits then 2 a locations are addressed v Data Bus: bi-directional bus ² Data can be transferred in both directions on the data bus v Control Bus ² Signals control transfer of data ² Read request Processor Memory address bus Address Register a bits data bus Data Register d bits ² Write request ² Done transfer Introduction 0 1 2 3 read COE 301– KFUPM . . . write Bus Control done slide 20 2 a – 1

Memory Devices v Volatile Memory Devices ² Data is lost when device is powered off ² RAM = Random Access Memory ² DRAM = Dynamic RAM § 1 -Transistor cell + trench capacitor § Dense but slow, must be refreshed § Typical choice for main memory ² SRAM: Static RAM § 6 -Transistor cell, faster but less dense than DRAM § Typical choice for cache memory v Non-Volatile Memory Devices ² ² ² Introduction Stores information permanently ROM = Read Only Memory Used to store the information required to startup the computer Many types: ROM, EPROM, EEPROM, and FLASH memory can be erased electrically in blocks COE 301– KFUPM slide 21

Magnetic Disk Storage A Magnetic disk consists of a collection of platters Provides a number of recording surfaces Read/write head Actuator Recording area Arm provides read/write heads for all surfaces The disk heads are connected together and move in conjunction Introduction COE 301– KFUPM Track 2 Track 1 Track 0 Arm Direction of rotation slide 22 Platter Spindle

Magnetic Disk Storage Sector Disk Access Time = Seek Time + Rotation Latency + Transfer. Read/write Time head Actuator Recording area Seek Time: head movement to the desired track (milliseconds) Rotation Latency: disk rotation until desired sector arrives under the head Transfer Time: to transfer data Introduction COE 301– KFUPM Track 2 Track 1 Track 0 Arm Direction of rotation slide 23 Platter Spindle

Example on Disk Access Time v Given a magnetic disk with the following properties ² Rotation speed = 7200 RPM (rotations per minute) ² Average seek = 8 ms, Sector = 512 bytes, Track = 200 sectors v Calculate ² Time of one rotation (in milliseconds) ² Average time to access a block of 32 consecutive sectors v Answer ² Rotations per second = 7200/60 = 120 RPS ² Rotation time in milliseconds = 1000/120 = 8. 33 ms ² Average rotational latency = time of half rotation = 4. 17 ms ² Time to transfer 32 sectors = (32/200) * 8. 33 = 1. 33 ms ² Average access time = 8 + 4. 17 + 1. 33 = 13. 5 ms Introduction COE 301– KFUPM slide 24

Processor-Memory Performance Gap CPU: 55% per year Performance 1000 “Moore’s Law” 100 Processor-Memory Performance Gap: (grows 50% per year) 10 DRAM: 7% per year 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 1 v 1980 – No cache in microprocessor v 1995 – Two-level cache on microprocessor Introduction COE 301– KFUPM slide 25

The Need for a Memory Hierarchy v Widening speed gap between CPU and main memory ² Processor operation takes less than 1 ns ² Main memory requires more than 50 ns to access v Each instruction involves at least one memory access ² One memory access to fetch the instruction ² A second memory access for load and store instructions v Memory bandwidth limits the instruction execution rate v Cache memory can help bridge the CPU-memory gap v Cache memory is small in size but fast Introduction COE 301– KFUPM slide 26

Typical Memory Hierarchy v Registers are at the top of the hierarchy ² Typical size < 1 KB Microprocessor ² Access time: 0. 5 – 1 ns Registers v L 2 Cache (64 KB – 8 MB) L 1 Cache ² Access time: 2 – 10 ns L 2 Cache v Main Memory (1 – 64 GB) Faster v Level 1 Cache (8 – 64 KB) Memory Bus ² Access time: 50 – 70 ns Memory v Disk Storage (> 200 GB) I/O Bus Disk, Tape, etc ² Access time: milliseconds Introduction COE 301– KFUPM slide 27 Bigger ² Access time < 0. 5 ns

Processor v Datapath: part of a processor that executes instructions v Control: generates control signals for each instruction Instruction Cache Instruction Program Counter Next Program Counter Registers Control Introduction COE 301– KFUPM slide 28 A L U Data Cache

Datapath Components v Program Counter (PC) ² Contains address of instruction to be fetched ² Next Program Counter: computes address of next instruction v Instruction Register (IR) ² Stores the fetched instruction v Instruction and Data Caches ² Small and fast memory containing most recent instructions/data v Register File ² General-purpose registers used for intermediate computations v ALU = Arithmetic and Logic Unit ² Executes arithmetic and logic instructions v Buses ² Used to wire and interconnect the various components Introduction COE 301– KFUPM slide 29

Infinite Cycle implemented in Hardware Fetch - Execute Cycle Introduction Instruction Fetch Instruction Decode Execute Fetch instruction Compute address of next instruction Generate control signals for instruction Read operands from registers Compute result value Memory Access Read or write memory (load/store) Writeback Result Writeback result in a register COE 301– KFUPM slide 30

Next. . . v Assembly-, Machine-, and High-Level Languages v Components of a Computer System v Technology Improvements v Programmer’s View of a Computer System Introduction COE 301– KFUPM slide 31

Technology Improvements v Vacuum tube → transistor → IC → VLSI v Processor ² Transistor count: about 30% to 40% per year v Memory ² DRAM capacity: about 60% per year (4 x every 3 yrs) ² Cost per bit: decreases about 25% per year v Disk ² Capacity: about 60% per year v Opportunities for new applications v Better organizations and designs Introduction COE 301– KFUPM slide 32

Growth of Capacity per DRAM Chip v DRAM capacity quadrupled almost every 3 years ² 60% increase per year, for 20 years Introduction COE 301– KFUPM slide 33

Processor Performance Slowed down by power and memory latency Almost 10000 x improvement between 1978 and 2005 Introduction COE 301– KFUPM slide 34

Next. . . v Assembly-, Machine-, and High-Level Languages v Components of a Computer System v Technology Improvements v Programmer’s View of a Computer System Introduction COE 301– KFUPM slide 35

Programmer’s View of a Computer System Software Application Programs High-Level Language Level 5 Assembly Language Level 4 Operating System Interface SW & HW Level 3 Instruction Set Architecture Level 2 Microarchitecture Level 1 Hardware Physical Design Introduction COE 301– KFUPM Increased level of abstraction Level 0 slide 36 Each level hides the details of the level below it

Programmer’s View of a Computer System v Application Programs (Level 5) ² Written in high-level programming languages ² Such as Java, C++, Pascal, Visual Basic. . . ² Programs compile into assembly language level (Level 4) v Assembly Language (Level 4) ² Instruction mnemonics (symbols) are used ² Have one-to-one correspondence to machine language ² Calls functions written at the operating system level (Level 3) ² Programs are translated into machine language (Level 2) Introduction COE 301– KFUPM slide 37

Programmer’s View of a Computer System v Operating System (Level 3) ² Provides services to level 4 and 5 programs ² Translated to run at the machine instruction level (Level 2) v Instruction Set Architecture (Level 2) ² Interface between software and hardware ² Specifies how a processor functions ² Machine instructions, registers, and memory are exposed ² Machine language is executed by Level 1 (microarchitecture) Introduction COE 301– KFUPM slide 38

Programmer’s View of a Computer System v Microarchitecture (Level 1) ² Controls the execution of machine instructions (Level 2) ² Implemented by digital logic v Physical Design (Level 0) ² Implements the microarchitecture at the transistor-level ² Physical layout of circuits on a chip Introduction COE 301– KFUPM slide 39