Interrupts 322021 1 What is an Interrupt n

Interrupts 3/2/2021 1

What is an Interrupt ? n n n Interrupt is a process where an external device can get the attention of the microprocessor. - the process start from the I/O devices - the process is asynchronous An interrupt is considered to be an emergency signal that may be serviced. The microprocessor may respond to it as soon as possible. 3/2/2021 2

What is an Interrupt ? n A hardware interrupt is a CPU facility which permits spurious asynchronous events to suspend program execution and instead execute a software module to service the event. n The connection to the processor which allows external devices to signal a request for service is called an interrupt pin. n The software module that the processor executes in response to an interrupt is called an interrupt service routine ( ISR ). n The interrupt mechanism is such that after completion of the ISR the processor returns to execution of the main program from the point at which it was interrupted. 3/2/2021 3

What happen when μP is interrupted? n n When the Microprocessor receive an interrupt signal, it suspend the currently executing program and jumps to an Interrupt Service Routine (ISR) to respond to the incoming interrupt. Each interrupt will most probably have its own ISR. 3/2/2021 4

Interrupt Event Sequence 3/2/2021 5

Classification of Interrupt n Interrupt can be classified into two types: q q n Maskable Interrupt (can be delayed or rejected) Nonmaskable interrupt (response the request immediately) Interrupts can also be classified into: q q 3/2/2021 Direct - the address of the service routine is already known to the microprocessor Vector - the address of the service routine need to be supplied externally by the device 6

Direct and Vectored Interrupts n With direct interrupts, the interrupting device need to provide the interrupt signal only. i. e. to assert the signal to the interrupt pin of the processor. n With direct interrupts the address of the first instruction of the ISR for the particular interrupt is pre-programmed into the CPU. n With vectored interrupts the interrupting device has to supply both the interrupt signal and the 16 -bit address of the first instruction of the ISR. n Interrupt service routines (ISR) for vectored interrupts can reside anywhere in the memory map of the computer system. 3/2/2021 7

Maskable and Non-maskable Interrupts n A non-maskable interrupt will always, if asserted, interrupt the processor. There is no software mechanism to prevent the processor being interrupted by a non-maskable interrupt. n A maskable interrupt, if asserted, will only interrupt the processor if it is enabled ( unmasked ). Maskable interrupts can be enabled ( unmasked ) or disabled ( masked ) by software. n Most maskable interrupts automatically become disabled (masked) after an interrupt has occurred. It requires further software commands to re-enable maskable interrupts. 3/2/2021 8

Interrupt Priority n n n For processor with multiple interrupt input pins, the various interrupts are assigned a priority. When simultaneous interrupts occur the highest priority interrupt will be serviced before lower priority interrupts. It is possible to arrange software such that whilst a lower priority interrupt is being serviced that a higher priority interrupt can interrupt the lower priority service routine. 3/2/2021 9

8085 A Interrupts 3/2/2021 10

Interrupt Trigger Type Trap RST 7. 5 RST 6. 5 RST 5. 5 INTR Rising Edge AND High Level Rising Edge High Level • • • Rising edge and high level – the input should go high and stay high to acknowledge. Rising edge/postive edge – can be triggered with a short pulse. High level – the triggering level should be on until the MP completes the execution of the current instruction. 3/2/2021 11

Enabling and Disabling Maskable Interrupts n n n 3/2/2021 The DI (disable interrupts) instruction disables all maskable interrupts. The EI (enable interrupts) instruction enables the vectored interrupt INTR and the unmasked restart interrupts RST 5. 5, RST 6. 5 and RST 7. 5. The interrupt mask for the restart interrupts is determined by the contents of the accumulator when the SIM (Set Interrupt Mask) instruction is executed. 12

How SIM Interprets the Accumulator? 6 5 4 3 2 1 0 SDO SDE XXX R 7. 5 MSE M 7. 5 M 6. 5 M 5. 5 7 Serial Data Out Enable Serial Data 0 - Ignore bit 7 1 - Send bit 7 to SOD pin Ignored RST 5. 5 Mask RST 6. 5 Mask RST 7. 5 Mask } 0 - Available 1 - Masked Mask Set Enable 0 - Ignore bits 0 -2 1 - Set the masks according to bits 0 -2 Reset RST 7. 5 If 1, RST 7. 5 flip flop is reset OFF Taken from : www. ee. hacettepe. edu. tr/~kenan/ele 415/interrupt. ppt 3/2/2021 13

Using the SIM Instruction to Modify the Interrupt Masks Example: Set the interrupt masks so that RST 5. 5 is enabled, RST 6. 5 is masked, and RST 7. 5 is enabled. q First, determine the contents of the accumulator - Enable 5. 5 - Disable 6. 5 - Enable 7. 5 - Allow setting the masks - Don’t reset the flip flop - Bit 5 is not used - Don’t use serial data - Serial data is ignored EI MVI A, 0 A SIM bit 0 = 0 bit 1 = 1 bit 2 = 0 bit 3 = 1 bit 4 = 0 bit 5 = 0 bit 6 = 0 bit 7 = 0 SDO SDE XXX R 7. 5 MSE M 7. 5 M 6. 5 M 5. 5 n 0 0 1 0 Contents of accumulator are: 0 AH ; Enable interrupts including INTR ; Prepare the mask to enable RST 7. 5, and 5. 5, disable 6. 5 ; Apply the settings RST masks Taken from : www. ee. hacettepe. edu. tr/~kenan/ele 415/interrupt. ppt 3/2/2021 14

EXAMPLE (Enable/Disable Direct Interrupt) For example to enable RST 7. 5 and RST 5. 5 and disable RST 6. 5 MVI A, 00011010 B SIM EI 3/2/2021 ; Set Interrupt Mask ; Enable Interrupt 15

ORG 0000 H JMP START ORG 0034 H JMP ISR 65 ORG 003 CH JMP ISR 75 START: …. MVI A, 00011001 B SIM EI …. . ISR 65: ISR 75: 3/2/2021 …. . RET 16

Machine Cycles with Direct Interrupts n n Since there is no requirement to supply ISR addresses with direct interrupts ( TRAP, RST 5. 5, RST 6. 5 & RST 7. 5 ) then there is no requirement for the 8085 A to execute INA machine cycles in response to such interrupts. However to provide the CPU sufficient time to process a direct interrupt, a six T-state bus idle machine cycle is introduced, following recognition of the direct interrupt. 3/2/2021 17

Machine Cycles with Direct Interrupts n n n During the bus idle machine cycle no control signal is asserted nor is the program counter incremented. Ready line control is ignored during the bus idle cycle. Following the bus idle cycle, two memory write cycles are executed to save the current contents of the program counter on the stack. The program counter is then overwritten with the preprogrammed address for the particular interrupt source. 3/2/2021 18

Machine Cycles with Vectored Interrupts n The 8085 A processor executes a number of machine cycles, in response to a vectored interrupt (INTR), prior to execution of the first instruction of the interrupt service routine. n The processor completes the execution of the current instruction. (Note : The processor only samples the interrupt inputs in the last T-state of the last machine cycle in the current instruction cycle) n This has implication in system design as it means that the interrupt signal on INTR must remain in the asserted state for at least the longest instruction in the 8085 A instruction set to guarantee that the processor recognizes the interrupt. 3/2/2021 19

Machine Cycles with Vectored Interrupts n The processor then executes a six T-state interrupt acknowledge machine cycle ( the INTA machine cycle is similar to the opcode fetch machine cycle except that the program counter is not incremented and the INTA* control signal is asserted instead of RD*) n In response to the INTA* signal, the interrupting device need to place the opcode of an instruction onto the data bus ( called jamming ). n The processor reads the opcode in the normal manner and stores it in the instruction register. n The choice of opcode is restricted as it is necessary to automatically save the contents of the program counter to enable the program to return to the point in the software where it was interrupted. 3/2/2021 20

Machine Cycles with Vectored Interrupts (CALL) n The only viable choice of 8085 A instruction is either the CALL instruction or the RST n instruction. n The CALL instruction is a 3 -byte instruction with bytes 2 & 3 being the address of the first instruction of the subroutine ( in this case the interrupt service routine (ISR)). 3/2/2021 21

Machine Cycles with Vectored Interrupts (CALL) n Following decoding of the CALL opcode, the processor executes a further two interrupt acknowledge machine cycles to fetch the address of the start of the ISR. n It is incumbent on the interrupting device to place the low byte of the address of the ISR onto the data bus in response to the second INTA*control signal and the high byte of the address in response to the third INTA* signal. 3/2/2021 22

Machine Cycles with Vectored Interrupts (CALL) n The execution phase of the CALL instruction can now take place. n The processor firstly executes two memory write machine cycles to save the current contents of the program counter onto the stack. The address as to where in memory the contents of PC is to be saved is specified by the stack pointer register. n Finally the processor overwrites the contents of the program counter with the second and third bytes of the call instruction. n The next instruction the processor will execute will be the first instruction of the ISR. 3/2/2021 23

Vector Interrupts (RST n) n The Restart instruction, RST n, where 0 ≤ n ≤ 7 n 1 -byte CALL instruction that transfer the program execution to a specific location on page 00 H [1]. n Executed the same way as CALL instruction ((SP)-1) (PCH) ((SP)-2) (PCL) 3/2/2021 ((SP) – 2 (PC) 8*n 24

Vector Interrupts (RST n) n In respond to the INTA strobe, external logic places an RST n opcode on the data bus. n RST n has the following bit pattern 11 NNN 111 where n=NNN (3 bit binary number) and restart address is n * 8 For example if RST 1, NNN = 001 and restart address is 8 (RST 2 (address 10 H), RST 3 (address 18 H) etc) 3/2/2021 25

Past Exam Question n n Vectored interrupt can be implemented using RST n or CALL instruction. Describe in detail how it can be done (04/05). [6 marks] State all types of interrupt available on the 8085 up. Considering maskable interrupt, give a short description (with instruction as working example) of masking, unmasking and enabling process (03/04)(06/07). [4 marks] 3/2/2021 26

Past Exam Question n n Vector interrupt can be implement using RST instruction. Explain in detail how it can be done (06/07). [4 marks] Describe the operation done by the 8085 microprocessor after receiving an interrupt request (03/04). [4 marks] 3/2/2021 27

References 1. 3/2/2021 Microprocessor Architecture, Programming, and Applications with the 8085, 5 th Edition, Ramesh S. Gaonkar. 28