Interrupt Interrupts of 8051 l l l l

Interrupt

Interrupts of 8051 l l l l Introduction 8051 Interrupt organization Processing Interrupts Program Design Using Interrupts Timer Interrupts Serial Port Interrupts External Interrupts Interrupt Timings

Interrupt l l An interrupt is the occurrence of a condition--an event -- that cause a temporary suspension of a program while the event is serviced by another program (Interrupt Service Routine ISR or Interrupt Handler). Interrupt-Driven System-- gives the illusion of doing many things simultaneously, quick response to events, suitable for real-time control application.

8051 Interrupt Organization l l l 5 interrupt sources: 2 external, 2 timer, a serial port 2 programmable interrupt priority levels fixed interrupt polling sequence can be enabled or disabled IE (A 8 H), IP (B 8 H) for controlling interrupts

Enabling and Disabling Interrupts IE (Interrupt Enable Register A 8 H) l l l l l Bit IE. 7 IE. 6 IE. 5 IE. 4 IE. 3 IE. 2 IE. 1 IE. 0 Symbol Bit Address EA AFH AEH ET 2 ADH ES ACH ET 1 ABH EX 1 AAH ET 0 A 9 H EX 0 A 8 H Description (1=enable, 0=disable) Global enable/disable Undefined Enable timer 2 interrupt (8052) Enable serial port interrupt Enable timer 1 interrupt Enable external 1 interrupt Enable timer 0 interrupt Enable external 0 interrupt Two bits must be set to enable any interrupt: the individual enable bit and global enable bit SETB ET 1 SETB EA MOV IE, #1000 B

Interrupt Priority (IP, B 8 H) l l l l l Bit IP. 7 IP. 6 IP. 5 IP. 4 IP. 3 IP. 2 IP. 1 IP. 0 Symbol Bit Address PT 2 BDH PS BCH PT 1 BBH PX 1 BAH PT 0 B 9 H PX 0 B 8 H Description (1=high, 0=low priority) Undefined Priority for timer 2 interrupt (8052) Priority for serial port interrupt Priority for timer 1 interrupt Priority for external 1 interrupt Priority for timer 0 interrupt Priority for external 0 interrupt • 0= lower priority, 1= higher priority, reset IP=00 H • Lower priority ISR can be interrupted by a high priority interrupt. • A high priority ISR can not be interrupted.

Interrupt Flag Bits Interrupt Flag SFR Register & Bit Position ---------------------------------------External 0 IE 0 TCON. 1 External 1 IE 1 TCON. 3 Timer 1 TF 1 TCON. 7 Timer 0 TF 0 TCON. 5 Serial port TI SCON. 1 Serial Port RI SCON. 0 Timer 2 TF 2 T 2 CON. 7 (8052) Timer 2 EXF 2 T 2 CON. 6 (8052) The state of all interrupt sources is available through the respective flag bits in the SFRs. If any interrupt is disabled, an interrupt does not occur, but software can still test the interrupt flag.

Polling Sequence l l If two interrupts of the same priority occur simultaneously, a fixed polling sequence determines which is serviced first. The polling sequence is External 0 > Timer 0 > External 1 > Timer 1 > Serial Port > Timer 2

Program Design Using Interrupts l I/O event handling: – – – Polling: main program keeps checking the flag, waiting for the occurrence of the event. Inefficient in some cases. Interrupt-driven: CPU can handle other things without wasting time waiting for the event. Efficient, prompt if ISR is not so complex. Suitable for control application. I/O processor: dedicated processor to handle most of the I/O job without CPU intervention. Best but most expensive

Processing Interrupts l When an interrupt occurs and is accepted by the CPU, the main program is interrupted. The following actions occur: – – – l The current instruction completes execution. The PC is saved on the stack. The current interrupt status is saved internally. Interrupts are blocked at the level of the interrupt. The PC is loaded with the vector address of the ISR The ISR executes. The ISR finishes with an RETI instruction, which retrieves the old value of PC from the stack and restores the old interrupt status. Execution of the main program continues where it left off.

Interrupt Vectors l l Interrupt vector = the address of the start of the ISR. When vectoring to an interrupt, the flag causing the interrupt is automatically cleared by hardware. The exception is RI/TI and TF 2/EXF 2 which should be determined and cleared by software. Interrupt System Reset External 0 Timer 0 External 1 Timer 1 Serial Port Timer 2 Flag RST IE 0 TF 0 IE 1 TF 1 RI or TI TF 2 or EXF 2 Vector Address 0000 H (LJMP 0030 H) 0003 H 000 BH 0013 H 001 BH 0023 H 002 BH

8051 Program Design Using Interrupt MAIN: T 0 ISR: ORG LJMP ORG. . RETI 0000 H MAIN 000 BH T 0 ISR 0030 H ; T 0 ISR entry point ; above int vectors ; Timer 0 ISR ; return to main

Timer l The 8051 has two timers/counters, they can be used either as – – l Timers to generate a time delay Event counters to count events happening outside the microcontroller Both Timer 0 and Timer 1 are 16 bits wide – Since 8051 has an 8 -bit architecture, each 16 -bits timer is accessed as two separate registers of low byte (TLx) and high byte (THx)

Timer

Timer