Interrupt Chapter 10 Sepehr Naimi www Nicer Land

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Interrupt Chapter 10 Sepehr Naimi www. Nicer. Land. com

Interrupt Chapter 10 Sepehr Naimi www. Nicer. Land. com

Contents n n n n Polling Vs. interrupt Interrupt (Exception) in ARM FIQ interrupt

Contents n n n n Polling Vs. interrupt Interrupt (Exception) in ARM FIQ interrupt in Raspberry Pi ARM Cortex-A modes Privilege levels in ARM Steps in executing an interrupt Context switching Interrupt priorities 2

Polling Vs. Interrupt n Polling n Ties down the CPU n Interrupt n n

Polling Vs. Interrupt n Polling n Ties down the CPU n Interrupt n n n Efficient CPU use Has priority Can be masked 3

Interrupt in ARM CPSR: 4

Interrupt in ARM CPSR: 4

FIQ Signal in Raspberry Pi 5

FIQ Signal in Raspberry Pi 5

Cortex-A Processor Modes & Privileges 6

Cortex-A Processor Modes & Privileges 6

Privilege Importance n n Different programs should have different privileges Memory access example: n

Privilege Importance n n Different programs should have different privileges Memory access example: n n A user (application) program should have limited access to memory otherwise it can change the data for other programs and damages them or causes the system to crash OS should have access to different parts of memory to be able to allocate memory and free it. 7

Privileged vs. Unprivileged Privileged n n can execute all the ARM instructions has access

Privileged vs. Unprivileged Privileged n n can execute all the ARM instructions has access to all registers Unprivileged n n cannot execute some of the ARM instructions has no access to some registers such the special function registers 8

Privileged vs. Unprivileged Privileged n n has access to every region of memory has

Privileged vs. Unprivileged Privileged n n has access to every region of memory has access to system timer and system resources Unprivileged n n has limited access to some regions of memory. is blocked from accessing system timer and system control block 9

Privileged vs. Unprivileged Privileged n Interrupt handlers can be executed only in Privileged level

Privileged vs. Unprivileged Privileged n Interrupt handlers can be executed only in Privileged level Unprivileged n In Unprivileged mode, one can use SVC instruction to make a supervisor call to switch from Unprivileged level to Privileged level 10

Cortex-A Processor modes n n n n n User, System, Supervisor, Abort, Undefined, IRQ,

Cortex-A Processor modes n n n n n User, System, Supervisor, Abort, Undefined, IRQ, FIQ, Monitor, Hypervisor CPSR: 11

Processor Modes vs. Privileges 12

Processor Modes vs. Privileges 12

Privilege levels for different programs 13

Privilege levels for different programs 13

Mode and privilege changes n n n When the system resets, it is in

Mode and privilege changes n n n When the system resets, it is in Supervisor mode and it has the privilege to access the different parts of the system to initialize them. The OS changes the mode to User when it runs an Application program to limit the privilege of the Application program. Whenever an interrupt occurs or the Application makes a system call, the mode changes to a privileged mode and OS services the interrupt. 14

Context Switching in Cortex-A n Every The allregisters modes, mode, has except which its

Context Switching in Cortex-A n Every The allregisters modes, mode, has except which its own are user/system in stack gray pointer. boxes modes are So, there banked thereisare isa(the a. SPSR separate mode register has stack which its for own In System the general purpose registers the same as the Useris each mode register) used to save the value of the CPSR register. mode. 15

Processing interrupts in ARM n n n CPSR is saved in the SPSR of

Processing interrupts in ARM n n n CPSR is saved in the SPSR of the target mode. The mode is changed to the target mode. The IRQ interrupt is disabled by setting the I flag in CPSR. The current PC is stored in the LR register. The CPU mode changes to ARM mode. PC is loaded with the address of the ISR. 16

Processing interrupts in ARM (Cont. ) n n From the memory locations pointed to

Processing interrupts in ARM (Cont. ) n n From the memory locations pointed to by PC, the CPU starts to fetch and execute instructions belonging to the ISR program. When the return instruction is executed in the interrupt service routine, the PC register is loaded with the value of the LR and CPSR is loaded with the contents of SPSR. This changes the mode to its previous mode and makes the CPU run the code where it left off when interrupt occurred 17

Processing interrupts in ARM 18

Processing interrupts in ARM 18

Interrupt Priority 19

Interrupt Priority 19