Interchip Serial Communication SPI and I 2 C

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Inter-chip Serial Communication: SPI and I 2 C Computer Science & Engineering Department Arizona

Inter-chip Serial Communication: SPI and I 2 C Computer Science & Engineering Department Arizona State University Tempe, AZ 85287 Dr. Yann-Hang Lee yhlee@asu. edu 7/23

Serial Peripheral Interface (SPI) q A duplex, synchronous, serial communication between CPU and peripheral

Serial Peripheral Interface (SPI) q A duplex, synchronous, serial communication between CPU and peripheral devices v Master mode and slave mode v Bi-directional mode v Synchronous serial clock peripheral 1 q Signals: v MOSI: master out slave in v MISO: master in slave out v SS: select signal from master to slave v SCK: serial clock MOSI MISO SCK SS 1 SS 2 processor MOSI MISO SCK SS peripheral 2 set 9 -- 1

SPI Operation q Data registers in the master and the slave form a distributed

SPI Operation q Data registers in the master and the slave form a distributed register. q When a data transfer operation is performed, this distributed register is serially shifted by the SCK clock from the master q Can shift in burst mode transmit data reg MOSI shift reg. MISO receive data reg set 9 -- 2

CPOL and CPHA (Polarity and Phase) q CPHA=0 – the first edge on the

CPOL and CPHA (Polarity and Phase) q CPHA=0 – the first edge on the SCK line is used to clock the first data bit (the first bit of the data must be ready when selected) q CPHA=1 – if required, the first SCK edge before the first data bit becomes available at the data out pin set 9 -- 3

SPI Block Diagram set 9 -- 4

SPI Block Diagram set 9 -- 4

Queued SPI q Queues for transmitting and receiving data, and commands. q Programmable queue

Queued SPI q Queues for transmitting and receiving data, and commands. q Programmable queue to support up to 16 transfers without user intervention. q NEWQP: Start of queue pointer. This 4 -bit field points to the first entry in the RAM to be executed on initiating a transfer. q ENDQP: End of queue pointer. Points to the RAM entry that contains the last transfer description in the queue. q CPTQP: Completed queue entry pointer. Points to the RAM entry that contains the last command to have been completed. q Indirect read/write – QAR[ADDR] and QDR q Wraparound enabling, chip select, etc. set 9 -- 5

Control of SPI q Mode and status v mode: master or slave. v enable

Control of SPI q Mode and status v mode: master or slave. v enable v SPIF is asserted when the QSPI has completed all the commands in the queue. v transfer size, clock polarity and phase, baud rate v delays between serial transfers and clock signal q Interrupts v on SPIF v write collision in accessing RAM (by QSPI and CPU) v abort set 9 -- 6

Example 12 -bit QSPI Transfer q 0 x. B 308 QMR: set up 12

Example 12 -bit QSPI Transfer q 0 x. B 308 QMR: set up 12 -bit data words with the data shifted on the q q q falling clock edge, and a QSPI_CLK frequency of 4. 125 MHz (assuming a 66 -MHz internal bus clock). desired delays QDLYR. 0 x. D 00 F QIR to enable write collision, abort bus errors, and clear any interrupts. 0 x 0020 QAR to select the first command RAM entry. Write QDR with commands (e. g. 0 x 7 E 00, 0 x 7 D 00, 0 x 7 B 00, 0 x 7700) to set up four transfers for each chip select. The chip selects are active low. 0 x 0000 QAR to select the first transmit RAM entry. Write QDR with sixteen 12 -bit words of data. 0 x 0 F 00 QWR to set up a queue beginning at entry 0 and ending at entry 15. Set QDLYR[SPE] to enable the transfers. Wait until the transfers are complete. QIR[SPIF] is set when the transfers are complete. 0 x 0010 QAR to select the first receive RAM entry. Read QDR to get the received data for each transfer. set 9 -- 7

I 2 C protocol – Background q Inter-Integrated Circuit Protocol q I 2 C

I 2 C protocol – Background q Inter-Integrated Circuit Protocol q I 2 C is a low-bandwidth, short-distance, two-wire interface for communication amongst ICs and peripherals q Originally developed by Philips for TV circuits q Only two bus lines are required Ø The SDA(for data) and SCL(for clock) q Each device connected to the bus is software addressable v Devices can be 7 -bit or 10 -bit addressed set 9 -- 8

I 2 C Features q Simple master-slave relation amongst devices (either can be receiver

I 2 C Features q Simple master-slave relation amongst devices (either can be receiver or transmitter) q Multi-bus master collision detection and arbitration is supported q Serial, 8 -bit oriented, bi-directional data transfer can be achieved up to 100 kbit/s (and up to 3. 4 Mbit/s in the high speed mode) q Suppose Micro-controller A wants to send info to micro-controller B 1. A (master) addresses B(slave) 2. A (master-transmitter) sends data to B(slave-receiver) 3. A terminates the transfer q Suppose Micro-controller A wants to receive info from micro-controller B 1. A (master) addresses B(slave) 2. A (master-receiver) receives data from B(slave-transmitter) 3. A terminates the transfer set 9 -- 9

I 2 C Bit-Transfer q One clock pulse is generated for each data bit

I 2 C Bit-Transfer q One clock pulse is generated for each data bit that is transferred q Data Validity v The data on the SDA line must be stable during the HIGH(1) period of the clock. The data line(SDA) can change data only when the clock signal (SCL) is LOW(0) q Wired-and function v open-drain or opencollector set 9 -- 10

I 2 C START/STOP Conditions q START condition: Signals begin of transfer (occupies the

I 2 C START/STOP Conditions q START condition: Signals begin of transfer (occupies the bus) v A HIGH to LOW transition on the SDA line while the SCL is HIGH q STOP condition: Signals end of transfer (releases the bus) v A LOW to HIGH transition on the SDA line while the SCL is HIGH q Both these are always generated by the Master q Repeated START condition is allowed v Repeated start is used for changing the slave, or changing the direction of data transfer (Send/Receive) for the same slave set 9 -- 11

I 2 C Data Transfer q Every byte on the SDA line must be

I 2 C Data Transfer q Every byte on the SDA line must be 8 -bits long q Each byte must be followed by an acknowledgement from the receiver q Data byte is transferred bit-wise with the MSB as the first bit sent q A slave can force the master to wait by holding the clock line SCL LOW set 9 -- 12

Acknowledgement Scheme q The acknowledge-related clock-pulse is generated by the master q The transmitter

Acknowledgement Scheme q The acknowledge-related clock-pulse is generated by the master q The transmitter (master or slave) releases the SDA line i. e. SDA is HIGH for the ACK clock pulse q The receiver must pull-down the SDA line during the acknowledge clock pulse (stable LOW) during the HIGH period of the clock pulse set 9 -- 13

Acknowledgement Scheme q The receiver is obliged to generate an acknowledge after each byte

Acknowledgement Scheme q The receiver is obliged to generate an acknowledge after each byte received. q When a slave does not acknowledge slave address (when busy), it leaves the data line HIGH. The master then generates either STOP or attempts repeated START. q If a slave-receiver does ack the slave address, but some time later during the transfer can not receive more data (this is done by leaving SDA HIGH during the ack pulse), then the master either generates STOP or attempts repeated START. q If a master-receiver is involved in a transfer, it must signal the end of data to the slave-transmitter by not generating an ack on the last byte that was clocked out of the slave. The slave-transmitter must release the data line to allow the master to generate a STOP or repeated START condition. set 9 -- 14

Data Transfer With 7 -Bit Device Address q After START condition (S), a slave

Data Transfer With 7 -Bit Device Address q After START condition (S), a slave address(7 -bit) is sent. q A read/write (R/W’) direction is then sent(8 th bit) q Data transfer occurs, and then always terminated by STOP condition. However, repeated START conditions can occur. set 9 -- 15

Master-Transmitter to Slave-Receiver Data Transfer q In this, the transmission direction never changes. The

Master-Transmitter to Slave-Receiver Data Transfer q In this, the transmission direction never changes. The set-up and transfer is straight-forward set 9 -- 16

Master-Receiver and Slave-Transmitter Data Transfer q Master initiates the data transfer by generating the

Master-Receiver and Slave-Transmitter Data Transfer q Master initiates the data transfer by generating the START condition followed by the start byte (with read/write bit set to 1 i. e. read mode) q After the first ack from the slave, the direction of data changes and the master becomes receiver and slave transmitter. q The STOP condition is still generated by the master (master sends not-ACK before generating the STOP) set 9 -- 17

Read and Write in the Same Data Transfer q Change in direction of data

Read and Write in the Same Data Transfer q Change in direction of data transfer can happen by the master generating another START condition (called the repeated START condition) with the slave address repeated q If the master was a receiver prior to the change, then the master sends a not-ack (A’) before the repeated START condition set 9 -- 18

7 -Bit Addressing q The addressing info is contained in the first byte after

7 -Bit Addressing q The addressing info is contained in the first byte after the START condition q The first 7 bits contain the address and LSB contains the direction of transfer(R/W’ : 0 = write; 1= read) q When an address is sent, each device compares the first seven bits and considers itself addressed. q A slave address can be made up of a fixed and a programmable part v PCF 8575 set 9 -- 19

Multi-Master Clock Synchronization q In the I 2 C bus, clock synchronization is performed

Multi-Master Clock Synchronization q In the I 2 C bus, clock synchronization is performed using the wired-AND v If at least one master clock goes from HIGH to LOW, then the SCL is held LOW irrespective of the other masters’ clock. v The SCL line goes to a HIGH state only when all the master clocks are in HIGH. q The synchronized clock is generated with its LOW period determined by the device with the longest clock LOW period and its HIGH period determined by the one with the shortest clock HIGH period. set 9 -- 20

Multi-Master Arbitration Using the Clock Syn. q If more than one device is capable

Multi-Master Arbitration Using the Clock Syn. q If more than one device is capable of being a master, then an arbitration mechanism is needed to choose the master that takes control of the bus q Arbitration takes place on the SDA, while the SCL is at the HIGH line, v the master which transmits a HIGH level, v another master is transmitting LOW level will switch off its DATA output stage because the level on the bus does not correspond to its own level. set 9 -- 21

I 2 C Conclusion q Compared to other serial bus protocols like SPI and

I 2 C Conclusion q Compared to other serial bus protocols like SPI and Microwire v The pin (and connection) requirements are the least in I 2 C v The noise immunity is higher for I 2 C v There is a feedback to the transmitter (Ack signal) for conveying the success of the transfer v I 2 C now has fast and high speed modes of operation set 9 -- 22

I 2 C Programming in Coldfire 5211 q Software control all I 2 C

I 2 C Programming in Coldfire 5211 q Software control all I 2 C operations v Can be a master or slave set 9 -- 23

I 2 C Programming q Initialization v Set I 2 FDR[IC] to obtain I

I 2 C Programming q Initialization v Set I 2 FDR[IC] to obtain I 2 C_SCL frequency from the system bus clock. v Update the I 2 ADR to define its slave address. v Set I 2 CR[IEN] to enable the I 2 C bus interface system. v Modify the I 2 CR to select or deselect master/slave mode, transmit/receive mode, and interrupt-enable or not. q As a master-transmitter v test I 2 SR[IBB] to determine whether the serial bus is free. v If the bus is free (IBB = 0), the START signal and the first byte (the slave address) can be sent. (I 2 CR[MTSA] and I 2 DR for slave address and R/W) v transmits next byte by write to I 2 DR v To stop, check I 2 SR[RXAK] and, if received, change I 2 CR[MSTA] to 0 set 9 -- 24