Inter FPGA communication with the VFC Few examples
- Slides: 8
Inter FPGA communication with the VFC Few examples
Outline The VFC inter FPGA (BE-FE) communication channels VFC FE-FPGA communication examples MOPOS AWAKE Desired generic features as extrapolated from those examples Wire-Scanners needs: what is already covered Conclusons?
The MOPOS BE FE link GBT based links (1 VFC for 4 GEFE) Upstream: Latency deterministic streamer: continuous flow of data 8 X 13 bits @20 MHz (~65% of the available payload bandwidth) 10 Mbs modulated data stream from a Sigma Delta Downstream: Semi-static configurations implemented as direct bus transport
The AWAKE BE FE link Electrical custom link @10 Mbps Upstream: Data frame self triggered Configuration/status transmitted with the data frame but also on change Downstream: 32 bits of configuration
Desired features Slow control Latency deterministic triggers Configuration/Status feedback (readout) Better if implemented as “on request” block transfer. A direct Wish. Bone bus extension would have high latency on the read transactions: ~2. 5 us+2*Link-transport time (using a single lane) High bandwidth Streamer Asymmetry (ports and payload size configurable) to optimize the available bandwidth
What is already covered of the WS needs? Streamer Prom remote (re)programmer Burst/block reads (DMA? ) BE-FE mirroring of configurations GPIO replication
Conclusions? All this features uses the link(s) in a very application specific way The GBT link offers the main features we want for a FPGA-FPGA connection, like e. d. c. and latency determinism, with such a ease of use that the customization of the wrapping layer(s) isn’t an issue, especially with the relatively simple structures we have in a BE-FE approach For the VFC we plan to leave the handling of the links to the users, providing support in the form of a precompiled core.
