Integrated Circuits Costs IC cost Die cost Testing

Real World Examples Chip Metal Line Wafer. Defect Dies/ Yield Die Cost layers width

Learning Curve • “When volume doubles, cost reduces 10%” – Gordon Bell 1978 •

Pipelining: Its Natural! • Laundry Example • Ann, Brian, Cathy, Dave each have one

Sequential Laundry 6 PM 7 8 9 10 11 Midnight Time 30 40 20

Pipelined Laundry Start work ASAP 6 PM 7 8 9 10 11 Midnight Time

Pipelining Lessons 6 PM 7 8 9 Time T a s k O r

Computer Pipelines • Execute billions of instructions, so throughout is what matters • DLX

Example: MIPS ( DLX) Register-Register 31 26 25 Op 21 20 Rs 1 16

5 Steps of DLX Datapath Figure 3. 1, Page 130 Instruction Fetch Instr. Decode

Pipelined DLX Datapath Figure 3. 4, page 137 Instruction Fetch Instr. Decode Reg. Fetch

Visualizing Pipelining Figure 3. 3, Page 133 Time (clock cycles) I n s t

Its Not That Easy for Computers • Limits to pipelining: Hazards prevent next instruction

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Integrated Circuits Costs IC cost = Die cost + Testing cost + Packaging cost Final test yield Die cost = Wafer cost Dies per Wafer * Die yield Dies per wafer = š * ( Wafer_diam / 2)2 – š * Wafer_diam – Test dies Die Area ¦ 2 * Die Area { Defects_per_unit_area * Die_Area Die Cost goes roughly with die area 4 }

Real World Examples Chip Metal Line Wafer. Defect Dies/ Yield Die Cost layers width cost /cm 2 wafer 386 DX 71% $4 486 DX 2 3 54% $12 Power. PC 601 115 28% 2 0. 90 $900 1. 0 0. 80 $1200 4 $53 0. 80 $1700 1. 0 Area mm 2 43 360 81 1. 3 121

Learning Curve • “When volume doubles, cost reduces 10%” – Gordon Bell 1978 • Example: PCs v. Workstations 1990 1992 1994 PC 24 M 33 M 44 M WS. 41 M. 58 M. 68 M Ratio 59 57 65 • 65 x ~ 2^6 >. 9^6 = 0. 53 1997 65 M. 98 M 67

Pipelining: Its Natural! • Laundry Example • Ann, Brian, Cathy, Dave each have one load of clothes to wash, dry, and fold • Washer takes 30 minutes • Dryer takes 40 minutes A B C D

Sequential Laundry 6 PM 7 8 9 10 11 Midnight Time 30 40 20 T a s k O r d e r A B C D • Sequential laundry takes 6 hours for 4 loads • If they learned pipelining, how long would

Pipelined Laundry Start work ASAP 6 PM 7 8 9 10 11 Midnight Time 30 40 T a s k O r d e r 40 40 40 20 A B C D • Pipelined laundry takes 3. 5 hours for 4 loads

Pipelining Lessons 6 PM 7 8 9 Time T a s k O r d e r 30 40 A B C D 40 40 40 20 • Pipelining doesn’t help latency of single task, it helps throughput of entire workload • Pipeline rate limited by slowest pipeline stage • Multiple tasks operating simultaneously

Computer Pipelines • Execute billions of instructions, so throughout is what matters • DLX desirable features: all instructions same length, registers located in same place in instruction format, memory operands only in loads or stores

Example: MIPS ( DLX) Register-Register 31 26 25 Op 21 20 Rs 1 16 15 Rs 2 11 10 6 5 Rd 0 Opx Register-Immediate 31 26 25 Op 21 20 Rs 1 16 15 0 immediate Rd Branch 31 26 25 Op Rs 1 21 20 16 15 Rs 2/Opx 0 immediate Jump / Call 31 26 25 Op 0 target

5 Steps of DLX Datapath Figure 3. 1, Page 130 Instruction Fetch Instr. Decode Reg. Fetch IR Execute Addr. Calc Memory Access Write Back L M D

Pipelined DLX Datapath Figure 3. 4, page 137 Instruction Fetch Instr. Decode Reg. Fetch Execute Addr. Calc. Write Back Memory Access • Data stationary control – local decode for each instruction phase / pipeline stage

Visualizing Pipelining Figure 3. 3, Page 133 Time (clock cycles) I n s t r. O r d e r

Its Not That Easy for Computers • Limits to pipelining: Hazards prevent next instruction from executing during its designated clock cycle – Structural hazards: HW cannot support this combination of instructions (single person to fold and put clothes away) – Data hazards: Instruction depends on result of prior instruction still in the pipeline (missing sock) – Control hazards: Pipelining of branches & other