Integrated Circuits A Design Perspective Jan M Rabaey
Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Inverter July 30, 2002 © Digital Integrated Circuits 2 nd Inverter
The CMOS Inverter: A First Glance V DD V in V out CL © Digital Integrated Circuits 2 nd Inverter
CMOS Inverter N Well VDD PMOS 2 l Contacts In Out Metal 1 Polysilicon NMOS GND © Digital Integrated Circuits 2 nd Inverter
Two Inverters Share power and ground Abut cells Connect in Metal © Digital Integrated Circuits 2 nd Inverter
CMOS Inverter First-Order DC Analysis V DD Rp V out VOL = 0 VOH = VDD VM = f(Rn, Rp) Rn V in 5 V DD © Digital Integrated Circuits 2 nd V in 5 0 Inverter
CMOS Inverter: Transient Response V DD tp. HL = f(Ron. CL) Rp = 0. 69 Ron. CL V out CL CL Rn V in 5 0 V in 5 V DD (a) Low-to-high (b) High-to-low © Digital Integrated Circuits 2 nd Inverter
Voltage Transfer Characteristi c © Digital Integrated Circuits 2 nd Inverter
PMOS Load Lines IDn V in = VDD +VGSp IDn = - IDp V out = VDD +VDSp Vout IDp Vin=0 IDn Vin=1. 5 VGSp=-1 VGSp=-2. 5 V DSp Vin = VDD+VGSp IDn = - IDp © Digital Integrated Circuits 2 nd Vin=0 Vin=1. 5 VDSp Vout = V DD+VDSp Inverter
CMOS Inverter Load Characteristics © Digital Integrated Circuits 2 nd Inverter
CMOS Inverter VTC © Digital Integrated Circuits 2 nd Inverter
function of Transistor Ratio 1. 8 1. 7 1. 6 1. 5 M V (V) 1. 4 1. 3 1. 2 1. 1 1 0. 9 0. 8 10 0 10 W /W © Digital Integrated Circuits 2 nd p n 1 Inverter
Determining VIH and VIL Vout V OH VM V in V OL V IH A simplified approach © Digital Integrated Circuits 2 nd Inverter
Inverter Gain © Digital Integrated Circuits 2 nd Inverter
Gain as a function of VDD Gain=-1 © Digital Integrated Circuits 2 nd Inverter
Simulated VTC © Digital Integrated Circuits 2 nd Inverter
Impact of Process Variations 2. 5 2 Good PMOS Bad NMOS Vout(V) 1. 5 Nominal 1 Good NMOS Bad PMOS 0. 5 0 0 0. 5 1 1. 5 2 2. 5 Vin (V) © Digital Integrated Circuits 2 nd Inverter
Propagation Delay © Digital Integrated Circuits 2 nd Inverter
Delay Approach 1 © Digital Integrated Circuits 2 nd Inverter
CMOS Inverter Propagation Delay Approach 2 © Digital Integrated Circuits 2 nd Inverter
CMOS Inverters VDD PMOS 1. 2 mm =2 l In Out Metal 1 Polysilicon NMOS GND © Digital Integrated Circuits 2 nd Inverter
Transient Response ? tp = 0. 69 CL (Reqn+Reqp)/2 tp. LH tp. HL © Digital Integrated Circuits 2 nd Inverter
Design for Performance q Keep capacitances small q Increase transistor sizes § watch out for self-loading! q Increase VDD (? ? ) © Digital Integrated Circuits 2 nd Inverter
Delay as a function of VDD © Digital Integrated Circuits 2 nd Inverter
Device Sizing (for fixed load) Self-loading effect: Intrinsic capacitances dominate © Digital Integrated Circuits 2 nd Inverter
NMOS/PMOS ratio tp. LH tp. HL tp © Digital Integrated Circuits 2 nd b = Wp/Wn Inverter
Impact of Rise Time on Delay © Digital Integrated Circuits 2 nd Inverter
Inverter Sizing © Digital Integrated Circuits 2 nd Inverter
Inverter Chain In Out CL If CL is given: - How many stages are needed to minimize the delay? - How to size the inverters? May need some additional constraints. © Digital Integrated Circuits 2 nd Inverter
Inverter Delay • Minimum length devices, L=0. 25 mm • Assume that for WP = 2 WN =2 W • same pull-up and pull-down currents • approx. equal resistances RN = RP • approx. equal rise tp. LH and fall tp. HL delays • Analyze as an RC network Delay (D): tp. HL = (ln 2) RNCL 2 W W tp. LH = (ln 2) RPCL Load for the next stage: © Digital Integrated Circuits 2 nd Inverter
Inverter with Load Delay RW CL RW Load (CL) t p = k R WC L k is a constant, equal to 0. 69 Assumptions: no load -> zero delay Wunit = 1 © Digital Integrated Circuits 2 nd Inverter
Inverter with Load CP = 2 Cunit Delay 2 W W Cint CN = Cunit CL Load Delay = k. RW(Cint + CL) = k. RWCint + k. RWCL = k. RW Cint(1+ CL /Cint) = Delay (Internal) + Delay (Load) © Digital Integrated Circuits 2 nd Inverter
Delay Formula Cint = g. Cgin with g 1 f = CL/Cgin - effective fanout R = Runit/W ; Cint =WCunit tp 0 = 0. 69 Runit. Cunit © Digital Integrated Circuits 2 nd Inverter
Apply to Inverter Chain In Out 1 2 N CL tp = tp 1 + tp 2 + …+ tp. N © Digital Integrated Circuits 2 nd Inverter
Optimal Tapering for Given N Delay equation has N - 1 unknowns, Cgin, 2 – Cgin, N Minimize the delay, find N - 1 partial derivatives Result: Cgin, j+1/Cgin, j = Cgin, j/Cgin, j-1 Size of each stage is the geometric mean of two neighbors - each stage has the same effective fanout (Cout/Cin) - each stage has the same delay © Digital Integrated Circuits 2 nd Inverter
Optimum Delay and Number of Stages When each stage is sized by f and has same eff. fanout f: Effective fanout of each stage: Minimum path delay © Digital Integrated Circuits 2 nd Inverter
Example In C 1 Out 1 f f 2 C L= 8 C 1 CL/C 1 has to be evenly distributed across N = 3 stages: © Digital Integrated Circuits 2 nd Inverter
Optimum Number of Stages For a given load, CL and given input capacitance Cin Find optimal sizing f For g = 0, f = e, N = ln. F © Digital Integrated Circuits 2 nd Inverter
Optimum Effective Fanout f Optimum f for given process defined by g fopt = 3. 6 for g=1 © Digital Integrated Circuits 2 nd Inverter
Impact of Self-Loading on tp No Self-Loading, g=0 © Digital Integrated Circuits 2 nd With Self-Loading g=1 Inverter
Normalized delay function of F © Digital Integrated Circuits 2 nd Inverter
Buffer Design 1 f tp 1 64 65 2 8 18 64 3 4 15 64 4 2. 8 15. 3 64 1 8 1 4 16 2. 8 8 1 N 64 22. 6 © Digital Integrated Circuits 2 nd Inverter
Power Dissipation © Digital Integrated Circuits 2 nd Inverter
Where Does Power Go in CMOS? © Digital Integrated Circuits 2 nd Inverter
Dynamic Power Dissipation Vdd Vin Vout CL Energy/transition = CL * Vdd 2 Power = Energy/transition * f = CL * Vdd 2 * f Not a function of transistor sizes! Need to reduce CL, Vdd, and f to reduce power. © Digital Integrated Circuits 2 nd Inverter
Modification for Circuits with Reduced Swing © Digital Integrated Circuits 2 nd Inverter
Adiabatic Charging 2 2 © Digital Integrated Circuits 2 nd 2 Inverter
Adiabatic Charging © Digital Integrated Circuits 2 nd Inverter
Node Transition Activity and Pow © Digital Integrated Circuits 2 nd Inverter
Transistor Sizing for Minimum Energy q Goal: Minimize Energy of whole circuit § Design parameters: f and VDD § tp tpref of circuit with f=1 and VDD =Vref © Digital Integrated Circuits 2 nd Inverter
Transistor Sizing (2) q Performance Constraint (g=1) q Energy for single Transition © Digital Integrated Circuits 2 nd Inverter
Transistor Sizing (3) VDD=f(f) E/Eref=f(f) F=1 2 5 10 20 © Digital Integrated Circuits 2 nd Inverter
Short Circuit Currents © Digital Integrated Circuits 2 nd Inverter
How to keep Short-Circuit Currents Low? Short circuit current goes to zero if tfall >> trise, but can’t do this for cascade logic, so. . . © Digital Integrated Circuits 2 nd Inverter
Minimizing Short-Circuit Power Vdd =3. 3 Vdd =2. 5 Vdd =1. 5 © Digital Integrated Circuits 2 nd Inverter
Leakage Sub-threshold current one of most compelling issues in low-energy circuit design! © Digital Integrated Circuits 2 nd Inverter
Reverse-Biased Diode Leakage JS = 10 -100 p. A/mm 2 at 25 deg C for 0. 25 mm CMOS JS doubles for every 9 deg C! © Digital Integrated Circuits 2 nd Inverter
Subthreshold Leakage Component © Digital Integrated Circuits 2 nd Inverter
Static Power Consumption Wasted energy … Should be avoided in almost all cases, but could help reducing energy in others (e. g. sense amps) © Digital Integrated Circuits 2 nd Inverter
Principles for Power Reduction q Prime choice: Reduce voltage! § Recent years have seen an acceleration in supply voltage reduction § Design at very low voltages still open question (0. 6 … 0. 9 V by 2010!) q Reduce switching activity q Reduce physical capacitance § Device Sizing: for F=20 – fopt(energy)=3. 53, fopt(performance)=4. 47 © Digital Integrated Circuits 2 nd Inverter
Impact of Technology Scaling © Digital Integrated Circuits 2 nd Inverter
Goals of Technology Scaling q Make things cheaper: § Want to sell more functions (transistors) per chip for the same money § Build same products cheaper, sell the same part for less money § Price of a transistor has to be reduced q But also want to be faster, smaller, lower power © Digital Integrated Circuits 2 nd Inverter
Technology Scaling q Goals of scaling the dimensions by 30%: § Reduce gate delay by 30% (increase operating frequency by 43%) § Double transistor density § Reduce energy per transition by 65% (50% power savings @ 43% increase in frequency Die size used to increase by 14% per generation q Technology generation spans 2 -3 years q © Digital Integrated Circuits 2 nd Inverter
Technology Generations © Digital Integrated Circuits 2 nd Inverter
Technology Evolution (2000 data) International Technology Roadmap for Semiconductors Year of Introduction 1999 Technology node [nm] 180 Supply [V] 2000 2001 2004 2008 2011 2014 130 90 60 40 30 0. 6 -0. 9 0. 5 -0. 6 0. 3 -0. 6 8 9 9 -10 10 3. 5 -2 7. 1 -2. 5 11 -3 14. 9 -3. 6 1. 5 -1. 8 1. 2 -1. 5 0. 9 -1. 2 Wiring levels 6 -7 7 Max frequency [GHz], Local-Global 1. 2 Max m. P power [W] 90 106 130 160 171 177 186 Bat. power [W] 1. 4 1. 7 2. 0 2. 4 2. 1 2. 3 2. 5 1. 6 -1. 4 2. 1 -1. 6 Node years: 2007/65 nm, 2010/45 nm, 2013/33 nm, 2016/23 nm © Digital Integrated Circuits 2 nd Inverter
Technology Evolution (1999) © Digital Integrated Circuits 2 nd Inverter
ITRS Technology Roadmap Acceleration Continues © Digital Integrated Circuits 2 nd Inverter
Technology Scaling (1) Minimum Feature Size © Digital Integrated Circuits 2 nd Inverter
Technology Scaling (2) Number of components per chip © Digital Integrated Circuits 2 nd Inverter
Technology Scaling (3) tp decreases by 13%/year 50% every 5 years! Propagation Delay © Digital Integrated Circuits 2 nd Inverter
Technology Scaling (4) From Kuroda © Digital Integrated Circuits 2 nd Inverter
Technology Scaling Models © Digital Integrated Circuits 2 nd Inverter
Scaling Relationships for Long Channel Devices © Digital Integrated Circuits 2 nd Inverter
Transistor Scaling (velocity-saturated devices) © Digital Integrated Circuits 2 nd Inverter
m. Processor Scaling P. Gelsinger: m. Processors for the New Millenium, ISSCC 2001 © Digital Integrated Circuits 2 nd Inverter
m. Processor Power P. Gelsinger: m. Processors for the New Millenium, ISSCC 2001 © Digital Integrated Circuits 2 nd Inverter
m. Processor Performance P. Gelsinger: m. Processors for the New Millenium, ISSCC 2001 © Digital Integrated Circuits 2 nd Inverter
2010 Outlook q Performance 2 X/16 months § 1 TIP (terra instructions/s) § 30 GHz clock q Size § No of transistors: 2 Billion § Die: 40*40 mm q Power § 10 k. W!! § Leakage: 1/3 active Power P. Gelsinger: m. Processors for the New Millenium, ISSCC 2001 © Digital Integrated Circuits 2 nd Inverter
Some interesting questions q What will cause this model to break? q When will it break? q Will the model gradually slow down? § Power and power density § Leakage § Process Variation © Digital Integrated Circuits 2 nd Inverter
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