Instructions Language of the Computer Patterson and Hennessy

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Instructions: Language of the Computer Patterson and Hennessy; Chapter 2

Instructions: Language of the Computer Patterson and Hennessy; Chapter 2

How is Information Stored in Memory? n Memory may be regarded as an array

How is Information Stored in Memory? n Memory may be regarded as an array of storage elements, each capable of storing a single byte. n n n 1 byte = 8 bits. Each memory element (i. e. each byte) has a unique address. Typically, information (instructions or data) is stored and exchanged as a collection of bytes called words. n n n 1 word = 2 – 8 bytes = 16 – 64 bits. The length of a word is machine specific and varies from one processor to another. The underlying hardware (e. g. buses, data ports, registers) must support the transfer of words.

q q q Assignment 1 is posted on Moodle. It is due 27 -2

q q q Assignment 1 is posted on Moodle. It is due 27 -2 -12 in class. Individual work.

Main Memory b Bits Chip Enable 01001101 0 11010100 1 10100010 2 N bits

Main Memory b Bits Chip Enable 01001101 0 11010100 1 10100010 2 N bits Address b bits 2 N words × b bits Data : : 00100001 2 N-1 Read / Write Address

Memory Organization b-Bit Word R 0 R 1 b-Bit Registers Memory R 2 R

Memory Organization b-Bit Word R 0 R 1 b-Bit Registers Memory R 2 R 3 Bytes Processor MDR b-Bit Bus

Memory Addresses n Every memory location is identified by a unique address. n n

Memory Addresses n Every memory location is identified by a unique address. n n n The number of bits used to represent an address determines the size of the address space. Assuming k address bits, it is possible to access 2 k separate memory locations whose address range = 0. . 2 k - 1. Standard memory sizes. n n 1 1 KB = 210 bytes. MB = 220 bytes. GB = 230 bytes. TB = 240 bytes.

Byte-Addressable Memory n In a byte-addressable memory, the smallest addressable unit of data is

Byte-Addressable Memory n In a byte-addressable memory, the smallest addressable unit of data is a byte. n n Successive bytes are assigned successive addresses: 0, 1, 2, 3, etc… Most computers are byte addressable. 8 bits Byte Address Byte 0 0 Byte 1 Byte 2 Byte 3 1 2 Byte 2 k-1 3 2 k-1

Word-Addressable Memory n In a word-addressable memory, the smallest addressable unit of data is

Word-Addressable Memory n In a word-addressable memory, the smallest addressable unit of data is a word. n n Word size is a machine-specific attribute. Words are typically power-of-two multiples of bytes (e. g. 2, 4, 8, or 16 bytes corresponding to 16 -, 32 -, 64 -, or 128 -bits, respectively). 32 bits Word Address Corresponding Byte Address Word 0 0 0 Word 1 Word 2 Word 3 1 2 4 8 3 12 Word 2 k-1 (2 k-1)*4

Word-Addressable Memory n Word-addressable memories are commonly built from byteaddressable memories. n n n

Word-Addressable Memory n Word-addressable memories are commonly built from byteaddressable memories. n n n 2 -byte (16 -bit) words are assigned addresses: 0, 2, 4, 6, 8, etc… 4 -byte (32 -bit) words are assigned addresses: 0, 4, 8, 12, 16, etc… 8 -byte (64 -bit) words are assigned addresses: 0, 8, 16, 24, 32, etc… Word 0 8 bits Byte Address Byte 0 0 Byte 1 Byte 2 Byte 3 1 2 3 4 5 6 Word 1 7 Byte 2 k-1 32 -Bit Word Address

Big- and Little-Endian Addressing n n Big-Endian: The most-significant bytes of a word are

Big- and Little-Endian Addressing n n Big-Endian: The most-significant bytes of a word are stored in lower byte addresses. Little-Endian: The least-significant bytes of a word are stored in lower byte addresses. MSB Byte Address LSB Byte Address MSB Address LSB 0 1 2 3 0 3 2 1 0 0 4 5 6 7 4 7 6 5 4 4 . . . 2 k-4 2 k-3 2 k-2 2 k-1 Big Endian Addressing . . . 2 k-4 2 k-1 2 k-2 2 k-3 2 k-4 Little Endian Addressing 2 k-4

Big- and Little-Endian Addressing n n n Example: F 498 B 70 FH Motorola

Big- and Little-Endian Addressing n n n Example: F 498 B 70 FH Motorola processors (e. g. MC 680 x 0) use Big Endian addressing. Intel processors (e. g. Pentium 4) use Little Endian addressing.

Word Alignment n A word is said to be aligned if it starts at

Word Alignment n A word is said to be aligned if it starts at a byte address that is a multiple of the number of bytes in the word. n n For a 32 -bit word, aligned addresses include: 0, 4, 8, etc… In some processors, attempting to access a non-aligned word from memory results in an error. In others, non-aligned memory accesses are acceptable.

Memory Contains Machine Instructions and Data 0 x 0000 ADD $T 0, $T 1,

Memory Contains Machine Instructions and Data 0 x 0000 ADD $T 0, $T 1, $T 2 0000000100101010010000100000 0 x 0004 0 x 0008 -11667 11111111101001001101101 0 x 000 C : : ’E’’E’’C’’E’ 010001010100001101000101 0 x. FFF 8 ’ 3’’ 2’’ 1’ 0000011000100100011 0 x. FFFC

Memory Map n To avoid mixing instructions, data, and restricted memory space, a memory

Memory Map n To avoid mixing instructions, data, and restricted memory space, a memory map is defined by system designers and (typically) managed by the operating system. n n The memory space is divided into regions that are each used for a dedicated purpose (e. g. storing application code, storing system code, storing static data, storing dynamic data, lookup tables, etc…). In general, the operating system is responsible for ensuring that memory map boundaries are respected.

Supporting Elementary Data Types n Numbers occupy one or more words in memory. n

Supporting Elementary Data Types n Numbers occupy one or more words in memory. n n n // single word // double word Characters occupy a single byte in memory. n n int sw; long int dw; char c; // single byte Strings occupy several bytes in memory. n char str[5] = {‘W’, ’o’, ’r’, ’d’, ’’}; // 5 bytes

Basic Processor Organization n Memory Address Register (MAR) n n Stores address of next

Basic Processor Organization n Memory Address Register (MAR) n n Stores address of next instruction to be fetched from memory. Instruction Register (IR) n n Stores data fetched from or sent to memory. Program Counter (PC) n n $R 0, 100($R 2) Main Memory Data Register (MDR) n n Stores address of next word to access from memory. LW Stores last instruction fetched from memory. Status Register (SR) n Stores processor status information (e. g. overflow, zero, carry out, interrupt masks). MAR MDR Control PC IR R 0 R 1. SR Processor . . Rn-1 ALU

Executing a Machine Instruction LW $R 0, 100($R 2) # $R 0 Memory [100

Executing a Machine Instruction LW $R 0, 100($R 2) # $R 0 Memory [100 + $R 2] T 1. T 2. T 3. MAR PC; Memory Read; PC + 4 MDR Memory [MAR] IR MDR T 4. T 5. T 6. MAR $R 2 + 100; Memory Read MDR Memory [MAR] $R 0 MDR n Fetch Execute How long does it take to fetch and execute this instruction?

Instruction Set Architecture defines n The set of machine instructions that a processor can

Instruction Set Architecture defines n The set of machine instructions that a processor can execute n n The number and type of operands a processor can operate on. n n constants, registers, or memory addresses. The different ways operands can be accessed. n n The instruction set. addressing modes. The width of the datapath. n Determines the size of elementary data types (e. g. int, double, float, etc…)

Architecture vs. Organization n Computer architecture: n n n Computer organization: n n That

Architecture vs. Organization n Computer architecture: n n n Computer organization: n n That part of a computer that is visible to the programmer/compiler. Includes the set of instructions (e. g. add, multiply, and shift), addressing modes, data width, and number and types of registers. That part of a computer that is transparent to the programmer. Includes the functional units (e. g. adders, multipliers, shifters), control mechanisms, memory hierarchy and organization, and communication mechanisms used to implement the architectural specification. Sometimes referred to as hardware implementation or microarchitecture. Families of computers may implement the same architecture but have different organizations (e. g. Intel 80 x 86).

Four Categories of Machine Instructions n Machine instructions can generally be divided into four

Four Categories of Machine Instructions n Machine instructions can generally be divided into four categories: n n Arithmetic and logic instructions; used to process data stored (mainly) in processor registers. Data transfer instructions; used to transfer data within the processor, or between the processor and memory. Program sequencing and control instructions; used to transfer control from one part of a program to another; also used to test for certain conditions. I/O transfer instructions; used to transfer data between the processor and an I/O device. In some processors, I/O transfer instructions are treated like data transfer instructions.

Assembly Language Notation n Used to describe machine instructions and programs. n n n

Assembly Language Notation n Used to describe machine instructions and programs. n n n Examples: Mnemonic n MIPS assembly Language Instructions are described using symbolic names called mnemonics. Operands are described using constants or symbolic names representing memory locations (i. e. memory addresses) or processor registers. n n Register operand Symbolic operand ADDI $R 4, $R 0, LABEL ORI SW $R 1, $R 2, 255 $R 5, 28($R 2) Comment # $R 4 LABEL+$R 0 # $R 1 $R 2 | 255 # Memory[28+$R 2] $R 5

Assembly Language Representations n Various forms of assembly language representations are common: n n

Assembly Language Representations n Various forms of assembly language representations are common: n n Three-address instructions. Two-address instructions. One-address instructions. Zero-address instructions.

Three-Address Instructions n Instructions are represented by an operation (mnemonic), two source operands, and

Three-Address Instructions n Instructions are represented by an operation (mnemonic), two source operands, and a destination operand. n n n The source operands may refer to constants, memory addresses, or processor registers. The destination operand typically refers to a processor register, but may also refer to a memory address. Example (MIPS R 2000): ADDI $R 1, $R 2, 100 # $R 1 $R 2 + 100

Register-Register Instruction Sets n Most modern (RISC: Reduced Instruction Set Computers) processors use three-address

Register-Register Instruction Sets n Most modern (RISC: Reduced Instruction Set Computers) processors use three-address instruction sets where source and destination operands are commonly stored in registers. n n n Operands stored in registers can be accessed much faster than operands stored in memory. Referred to as register-register instruction sets. Example: A = B + C LW LW ADD SW $R 1, 0($R 4) $R 2, 0($R 5) $R 3, $R 1, $R 2 $R 3, 0($R 6) # # Assume $R 4 contains &B Assume $R 5 contains &C $R 3 $R 1 + $R 2 Assume $R 6 contains &A

Two-Address Instructions n Instructions are represented by an operation (mnemonic), one source operand, and

Two-Address Instructions n Instructions are represented by an operation (mnemonic), one source operand, and one destination operand. n n In a two-address instruction, the destination is often an implicit source operand too. Example (MC 68000): ADD (A 0), D 1 ; D 1 Memory[A 0] + D 1 Destination Operand n Example (Intel 80 x 86) ADD AX, BX ; AX + BX

One-Address Instructions n Instructions are represented by an operation (mnemonic) and a single source

One-Address Instructions n Instructions are represented by an operation (mnemonic) and a single source operand. n n One-address instructions assume the presence of an implicit register called the accumulator, which is used both as a source and a destination. Example (PIC 16 F 84): ADDLW 100 ; W W + 100 In the PIC 16 F 84, the accumulator is called the working register (W).

Zero-Address Instructions n Zero-address instruction sets are used in stack-based architectures (e. g. the

Zero-Address Instructions n Zero-address instruction sets are used in stack-based architectures (e. g. the Java Virtual Machine – JVM). n n All machine instructions operate on data stored on top of the stack (TOS). Example: C = A + B ; Mem[TOS] A ; Mem[TOS] B ; Mem[TOS] Mem[TOS-1]+Mem[TOS] ; C Mem[TOS] PUSH A PUSH B ADD POP C All operands are implicit. TOS A+ B AB A

Instruction Execution n All instructions are executed in two phases: n n n Instruction

Instruction Execution n All instructions are executed in two phases: n n n Instruction fetch. n n n Fetch. Execute. IR Memory [PC]. Increment PC. Instruction execute. n n Decode instruction. Fetch operand(s). Execute operation. Store the result if the instruction generates one.

Instruction Execution Begin execution here Address Contents # A = B + C $R

Instruction Execution Begin execution here Address Contents # A = B + C $R 5, $ZERO, C ADDI $R 6, $ZERO, A LW $R 1, 0($R 4) LW $R 2, 0($R 5) ADD $R 3, $R 1, $R 2 SW $R 3, 0($R 6) … LW $R 1, 0($R 4) i+4 LW $R 2, 0($R 5) i+8 ADD $R 3, $R 1, $R 2 i+12 SW $R 3, 0($R 6) B . data A: . word 0 B: . word 10 C: . word 5 Program Segment for A=B+C A C Data for the program . . . ADDI i . . . $R 4, $ZERO, B . . . ADDI

Branch Instructions n Change program control flow by loading a new value in the

Branch Instructions n Change program control flow by loading a new value in the program counter (PC). n n Unconditional branches n n n The new address is called the branch target. Always executed. Example: J TARGET # PC TARGET Conditional branches n n Executed only if a certain condition is true. Otherwise, the instruction immediately following the conditional branch is fetched next. Example: BEQ $R 1, $R 2, TARGET # PC TARGET if $R 1 == $R 2

Branch instructions are commonly used to implement loops To place the address of an

Branch instructions are commonly used to implement loops To place the address of an array or a variable in a register LOOP: EXIT: int sum, coeffs[100]; sum = 0; for (i = 0; i < 100; i++) { sum = sum + coeffs[i]; } ADDI $R 1, $ZERO, coeffs # $R 1 &(coeffs[0]) ADDI $R 2, $ZERO, sum # $R 2 &sum ADDI $R 3, $ZERO, 100 # $R 3 100 ADD $R 4, $ZERO # $R 4 i; initialize to zero ADD $R 5, $ZERO # $R 5 temp; initialize to zero BEQ $R 3, $R 4, EXIT # if (i = = 100) exit the loop LW $R 6, 0($R 1) # $R 6 coeffs[i] ADD $R 5, $R 6 # temp + coeffs[i] ADDI $R 1, 4 # increment $R 1 ADDI $R 4, 1 # increment i J LOOP # goto LOOP SW $R 5, 0($R 2) # sum temp

Condition Codes n A collection of flags that track the results of previous instruction

Condition Codes n A collection of flags that track the results of previous instruction for use by subsequent conditional branch instructions. n n Common condition code flags n n n Typically stored in a special condition code register or a status register. N (negative) Z (zero) V (overflow) C (carry) = = 1 1 if if result is negative; 0 otherwise. result is zero; 0 otherwise. arithmetic overflow occurs; 0 otherwise. operation results in carry-out; 0 otherwise. Branch>0 instruction tests N and Z flags. n n TRUE if (N=0 AND Z=0); branch is said to be “taken”. FALSE if (N=1 OR Z=1); branch is said to be “not taken”.