inst eecs berkeley educs 61 csu 06 CS

inst. eecs. berkeley. edu/~cs 61 c/su 06 CS 61 C : Machine Structures Lecture #16 – Datapath 2006 -07 -25 Andy Carle CS 61 C L 16 Datapath (1) A Carle, Summer 2006 © UCB

Anatomy: 5 components of any Computer Personal Computer Processor This week Control (“brain”) Datapath (“brawn”) Memory (where programs, data live when running) Devices Input Output Keyboard, Mouse Disk (where programs, data live when not running) Display, Printer CS 61 C L 16 Datapath (2) A Carle, Summer 2006 © UCB

Outline • Design a processor: step-by-step • Requirements of the Instruction Set • Hardware components that match the instruction set requirements CS 61 C L 16 Datapath (3) A Carle, Summer 2006 © UCB

How to Design a Processor: step-by-step • 1. Analyze instruction set architecture (ISA) => datapath requirements • meaning of each instruction is given by the register transfers • datapath must include storage element for ISA registers • datapath must support each register transfer • 2. Select set of datapath components and establish clocking methodology • 3. Assemble datapath meeting requirements • 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. • 5. Assemble the control logic CS 61 C L 16 Datapath (4) A Carle, Summer 2006 © UCB

Step 1: The MIPS Instruction Formats • All MIPS instructions are 2132 bits long. 3 formats: 31 26 16 11 6 0 op • R-type 6 bits 31 • I-type • J-type rs 5 bits 26 op 6 bits 31 rt 5 bits 21 rs 5 bits rd shamt funct 5 bits 6 bits 16 rt 5 bits 26 op 6 bits • The different fields are: 0 address/immediate 16 bits 0 target address 26 bits • op: operation (“opcode”) of the instruction • rs, rt, rd: the source and destination register specifiers • shamt: shift amount • funct: selects the variant of the operation in the “op” field • address / immediate: address offset or immediate value • target address: target address of jump instruction CS 61 C L 16 Datapath (5) A Carle, Summer 2006 © UCB

Step 1: The MIPS-lite Subset for today • ADD and SUB 31 • add. U rd, rs, rt • sub. U rd, rs, rt • OR Immediate: • ori 26 op 6 bits 31 31 31 • BRANCH: 26 op 6 bits • beq rs, rt, imm 16 CS 61 C L 16 Datapath (6) rs 5 bits rt 5 bits 21 rs 5 bits rd 5 bits 6 shamt 5 bits funct 6 bits immediate 16 bits 0 immediate 16 bits 16 rt 5 bits 0 0 16 rt 5 bits 11 16 21 rs 6 bits 16 21 26 op • lw rt, rs, imm 16 • sw rt, rs, imm 16 rs 5 bits 26 op rt, rs, imm 166 bits • LOAD and STORE Word 21 0 immediate 16 bits A Carle, Summer 2006 © UCB

Step 1: Register Transfer Language • RTL gives the meaning of the instructions {op , rs , rt , rd , shamt , funct} = MEM[ PC ] {op , rs , rt , Imm 16} = MEM[ PC ] • All start by fetching the instruction inst Register Transfers ADDU R[rd] = R[rs] + R[rt]; PC = PC + 4 SUBU R[rd] = R[rs] – R[rt]; PC = PC + 4 ORI R[rt] = R[rs] | zero_ext(Imm 16); PC = PC + 4 LOAD R[rt] = MEM[ R[rs] + sign_ext(Imm 16)]; PC = PC + 4 STORE MEM[ R[rs] + sign_ext(Imm 16) ] = R[rt]; PC = PC + 4 BEQ CS 61 C L 16 Datapath (7) if ( R[rs] == R[rt] ) then PC = PC + 4 + sign_ext(Imm 16)] << 2 else PC = PC + 4 A Carle, Summer 2006 © UCB

Step 1: Requirements of the Instruction Set • Memory (MEM) • instructions & data • Registers (R: 32 x 32) • read RS • read RT • Write RT or RD • PC • Extender (sign extend) • Add and Sub register or extended immediate • Add 4 or extended immediate to PC CS 61 C L 16 Datapath (8) A Carle, Summer 2006 © UCB

Step 1: Abstract Implementation Control PC Clk Next Address ALU Ideal Instruction Control Signals Conditions Memory Rd Rs Rt 5 5 5 Instruction Address A Data 32 Address Rw Ra Rb 32 Ideal Out 32 32 -bit 32 Data Registers B Memory In Clk 32 Clk Datapath CS 61 C L 16 Datapath (9) A Carle, Summer 2006 © UCB

How to Design a Processor: step-by-step • 1. Analyze instruction set architecture (ISA) => datapath requirements • meaning of each instruction is given by the register transfers • datapath must include storage element for ISA registers • datapath must support each register transfer • 2. Select set of datapath components and establish clocking methodology • 3. Assemble datapath meeting requirements • 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. • 5. Assemble the control logic (hard part!) CS 61 C L 16 Datapath (10) A Carle, Summer 2006 © UCB

Step 2 a: Components of the Datapath • Combinational Elements • Storage Elements • Clocking methodology CS 61 C L 16 Datapath (11) A Carle, Summer 2006 © UCB

Combinational Logic: More Elements A B 32 Adder • Adder Carry. In 32 Sum Carry 32 Select B 32 MUX • MUX A 32 Y 32 OP A CS 61 C L 16 Datapath (12) B ALU • ALU 32 32 Result 32 A Carle, Summer 2006 © UCB

ALU Needs for MIPS-lite + Rest of MIPS • Addition, subtraction, logical OR, ==: ADDU R[rd] = R[rs] + R[rt]; . . . SUBU R[rd] = R[rs] – R[rt]; . . . ORI R[rt] = R[rs] | zero_ext(Imm 16). . . BEQ if ( R[rs] == R[rt] ). . . • Test to see if output == 0 for any ALU operation gives == test. How? • P&H also adds AND, Set Less Than (1 if A < B, 0 otherwise) • ALU follows chap 5 CS 61 C L 16 Datapath (13) A Carle, Summer 2006 © UCB

Storage Element: Idealized Memory Write Enable Address • Memory (idealized) Data In • One input bus: Data In 32 • One output bus: Data Out Clk Data. Out 32 • Memory word is selected by: • Address selects the word to put on Data Out • Write Enable = 1: address selects the memory word to be written via the Data In bus • Clock input (CLK) • The CLK input is a factor ONLY during write operation • During read operation, behaves as a combinational logic block: - Address valid => Data Out valid after “access time. ” CS 61 C L 16 Datapath (14) A Carle, Summer 2006 © UCB

Storage Element: Register (Building Block) • Similar to D Flip Flop except - N-bit input and output - Write Enable input • Write Enable: - negated (or deasserted) (0): Data Out will not change - asserted (1): Data Out will become Data In CS 61 C L 16 Datapath (15) Write Enable Data In N Data Out N Clk A Carle, Summer 2006 © UCB

Storage Element: Register File • Register File consists of 32 registers: • Two 32 -bit output busses: bus. A and bus. B • One 32 -bit input bus: bus. W • Register is selected by: RWRA RB Write Enable 5 5 5 bus. W 32 Clk bus. A 32 32 32 -bit Registers bus. B 32 • RA (number) selects the register to put on bus. A (data) • RB (number) selects the register to put on bus. B (data) • RW (number) selects the register to be written via bus. W (data) when Write Enable is 1 • Clock input (CLK) • The CLK input is a factor ONLY during write operation • During read operation, behaves as a combinational logic block: - RA or RB valid => bus. A or bus. B valid after “access time. ” CS 61 C L 16 Datapath (16) A Carle, Summer 2006 © UCB

Administrivia • Project 2 due Friday • Hope you’ve already started • HW 5 (maybe HW 56? ) out soon CS 61 C L 16 Datapath (17) A Carle, Summer 2006 © UCB

Step 3: Assemble Data. Path meeting requirements • Register Transfer Requirements Datapath Assembly • Instruction Fetch • Read Operands and Execute Operation CS 61 C L 16 Datapath (18) A Carle, Summer 2006 © UCB

3 a: Overview of the Instruction Fetch Unit • The common RTL operations • Fetch the Instruction: mem[PC] • Update the program counter: - Sequential Code: PC = PC + 4 - Branch and Jump: PC = “something else” Clk PC Next Address Logic Address Instruction Memory CS 61 C L 16 Datapath (19) Instruction Word 32 A Carle, Summer 2006 © UCB

3 b: Add & Subtract • R[rd] = R[rs] op R[rt] Ex. : add. U rd, rs, rt • Ra, Rb, and Rw come from instruction’s Rs, Rt, 26 21 16 11 6 and Rd fields 31 op 6 bits rs 5 bits rt 5 bits rd 5 bits shamt 5 bits funct 6 bits 0 • ALUctr and Reg. Wr: control logic after decoding the instruction Rd Rs Rt Reg. Wr 5 5 5 32 32 -bit Registers bus. A 32 bus. B 32 ALU bus. W 32 Clk Rw Ra Rb ALUctr Result 32 • Already defined register file, ALU CS 61 C L 16 Datapath (20) A Carle, Summer 2006 © UCB

Clocking Methodology Clk. . . • Storage elements clocked by same edge • Being physical devices, flip-flops (FF) and combinational logic have some delays • Gates: delay from input change to output change • Signals at FF D input must be stable before active clock edge to allow signal to travel within the FF, and we have the usual clock-to-Q delay • “Critical path” (longest path through logic) determines length of clock period CS 61 C L 16 Datapath (21) A Carle, Summer 2006 © UCB

Register-Register Timing: One complete cycle Clk New Value PC Old Value Instruction Memory Access Time Rs, Rt, Rd, Old Value New Value Op, Func Delay through Control Logic ALUctr Old Value New Value Reg. Wr Old Value bus. A, B Old Value bus. W Old Value New Value Register File Access Time New Value ALU Delay New Value Rd Rs Rt Reg. Wr 5 5 5 CS 61 C L 16 Datapath (22) bus. A 32 bus. B 32 ALU bus. W 32 Clk Rw Ra Rb 32 32 -bit Registers ALUctr Register Write Occurs Here Result 32 A Carle, Summer 2006 © UCB

3 c: Logical Operations with Immediate • R[rt] = R[rs] op Zero. Ext[imm 16] ] 31 26 21 op 31 6 bits Rd Rt Reg. Dst Mux Rs Rt? Reg. Wr 5 5 5 32 Clk What about Rt register read? ? ALUct r bus. A 32 bus. B 32 Result 32 32 ALUSrc • Already defined 32 -bit MUX; Zero Ext? CS 61 C L 16 Datapath (23) 0 Mux 16 0 rt immediate 5 bits 16 15 rd? 16 bits immediate 00000000 16 bits Zero. Ext imm 16 11 rs 5 bits ALU bus. W Rw Ra Rb 32 32 -bit Registers 16 A Carle, Summer 2006 © UCB

3 d: Load Operations • R[rt] = Mem[R[rs] + Sign. Ext[imm 16]] Example: lw rt, rs, imm 16 31 26 op 6 bits Rd Reg. Dst Mux Reg. Wr 5 32 Clk rs 5 bits 0 rt 5 bits immediate 16 bits Rt Rs Rt 5 5 Rw Ra Rb 32 32 -bit Registers W_Src 32 bus. B 32 32 Ext. Op 32 Mem. Wr ? ? ALUSrc Data In 32 Clk Mux CS 61 C L 16 Datapath (24) bus. A Mux 16 ALUctr Extender imm 16 16 ALU bus. W 21 Wr. En Adr Data Memory 32 A Carle, Summer 2006 © UCB

3 e: Store Operations • Mem[ R[rs] + Sign. Ext[imm 16] ] = R[rt] Ex. : sw rt, rs, imm 16 31 26 21 op rs 6 bits 5 bits Rd Rt Reg. Dst Mux Reg. Wr 5 rt 5 bits immediate 16 bits ALUctr Mem. Wr W_Src 32 Ext. Op CS 61 C L 16 Datapath (25) 32 Data In 32 Clk Wr. En. Adr 32 Data Memory Mux Extender 16 ALU bus. A Rw Ra Rb 32 32 32 -bit Registers bus. B 32 imm 16 0 Rs Rt 5 5 Mux bus. W 32 Clk 16 ALUSrc A Carle, Summer 2006 © UCB

3 f: The Branch Instruction 31 26 op 6 bits 21 rs 5 bits 16 rt 5 bits 0 immediate 16 bits • beq rs, rt, imm 16 • mem[PC] Fetch the instruction from memory • Equal = R[rs] == R[rt] Calculate branch condition • if (Equal) Calculate the next instruction’s address - PC = PC + 4 + ( Sign. Ext(imm 16) x 4 ) else - PC = PC + 4 CS 61 C L 16 Datapath (26) A Carle, Summer 2006 © UCB

Datapath for Branch Operations • beq rs, rt, imm 16 Datapath generates condition (equal) 26 op 6 bits 21 rs 5 bits 00 Adder 32 PC Mux Adder PC Ext imm 16 0 immediate rt 5 bits 16 bits Inst Address n. PC_sel 4 16 Rs Rt 5 5 bus. A Rw Ra Rb 32 32 32 -bit Registers bus. B 32 Cond Reg. Wr 5 bus. W Clk Equal? 31 Clk • Already MUX, adder, sign extend, zero CS 61 C L 16 Datapath (27) A Carle, Summer 2006 © UCB

Putting it All Together: A Single Cycle Datapath Instruction<31: 0> <0: 15> <11: 15> Rs <16: 20> <21: 25> Inst Memory Adr Rt Rd Imm 16 Reg. Dst ALUctr Mem. Wr Memto. Reg Equal Rt Rd 1 0 Rs Rt Reg. Wr 5 5 5 bus. A Rw Ra Rb = bus. W 32 32 32 -bit 0 32 32 Registers bus. B 0 32 Clk 32 Wr. En. Adr 1 1 Data In Data imm 16 32 Clk 16 Clk Memory n. PC_sel imm 16 Mux ALU Extender PC Ext Adder Mux PC Mux Adder 00 4 Ext. Op ALUSrc CS 61 C L 16 Datapath (28) A Carle, Summer 2006 © UCB

Peer Instruction A. Our ALU is a synchronous device B. We should use the main ALU to compute PC=PC+4 C. The ALU is inactive for memory reads or writes. CS 61 C L 16 Datapath (29) A Carle, Summer 2006 © UCB

Summary: Single cycle datapath ° 5 steps to design a processor • 1. Analyze instruction set => datapath requirements • 2. Select set of datapath components & establish clock methodology • 3. Assemble datapath meeting the requirements • 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. Processor • 5. Assemble the control logic ° Control is the hard part ° Next time! CS 61 C L 16 Datapath (30) Input Control Memory Datapath Output A Carle, Summer 2006 © UCB