inst eecs berkeley educs 61 c UC Berkeley

  • Slides: 25
Download presentation
inst. eecs. berkeley. edu/~cs 61 c UC Berkeley CS 61 C : Machine Structures

inst. eecs. berkeley. edu/~cs 61 c UC Berkeley CS 61 C : Machine Structures Lecture 23 – Representations of Combinational Logic Circuits 2011 -10 -24 Lecturer SOE Dan Garcia www. cs. berkeley. edu/~ddgarcia Android Brain on Robots! “Half the weight of some robots is due to on-board computers and the batteries needed to power them. This lightweight robot uses an Android phone as the brain, with the phone’s gyroscope and camera as sensors, with cloud help!” www. technologyreview. com/business/38953/page 1/ CS 61 C L 25 Representations of Combinational Logic Circuits (1) Garcia, Fall 2011 © UCB

Review • State elements are used to: • Build memories • Control the flow

Review • State elements are used to: • Build memories • Control the flow of information between other state elements and combinational logic • D-flip-flops used to build registers • Clocks tell us when D-flip-flops change • Setup and Hold times important • We pipeline long-delay CL for faster clock • Finite State Machines extremely useful • Represent states and transitions CS 61 C L 25 Representations of Combinational Logic Circuits (2) Garcia, Fall 2011 © UCB

Truth Tables 0 CS 61 C L 25 Representations of Combinational Logic Circuits (3)

Truth Tables 0 CS 61 C L 25 Representations of Combinational Logic Circuits (3) Garcia, Fall 2011 © UCB

TT Example #1: 1 iff one (not both) a, b=1 a 0 0 1

TT Example #1: 1 iff one (not both) a, b=1 a 0 0 1 1 b 0 1 CS 61 C L 25 Representations of Combinational Logic Circuits (4) y 0 1 1 0 Garcia, Fall 2011 © UCB

TT Example #2: 2 -bit adder How Many Rows? CS 61 C L 25

TT Example #2: 2 -bit adder How Many Rows? CS 61 C L 25 Representations of Combinational Logic Circuits (5) Garcia, Fall 2011 © UCB

TT Example #3: 32 -bit unsigned adder How Many Rows? CS 61 C L

TT Example #3: 32 -bit unsigned adder How Many Rows? CS 61 C L 25 Representations of Combinational Logic Circuits (6) Garcia, Fall 2011 © UCB

TT Example #4: 3 -input majority circuit CS 61 C L 25 Representations of

TT Example #4: 3 -input majority circuit CS 61 C L 25 Representations of Combinational Logic Circuits (7) Garcia, Fall 2011 © UCB

Logic Gates (1/2) CS 61 C L 25 Representations of Combinational Logic Circuits (8)

Logic Gates (1/2) CS 61 C L 25 Representations of Combinational Logic Circuits (8) Garcia, Fall 2011 © UCB

And vs. Or review – Dan’s mnemonic AND Gate Symbol A B AN D

And vs. Or review – Dan’s mnemonic AND Gate Symbol A B AN D Definition C CS 61 C L 25 Representations of Combinational Logic Circuits (9) Garcia, Fall 2011 © UCB

Logic Gates (2/2) CS 61 C L 25 Representations of Combinational Logic Circuits (10)

Logic Gates (2/2) CS 61 C L 25 Representations of Combinational Logic Circuits (10) Garcia, Fall 2011 © UCB

2 -input gates extend to n-inputs • N-input XOR is the only one which

2 -input gates extend to n-inputs • N-input XOR is the only one which isn’t so obvious • It’s simple: XOR is a 1 iff the # of 1 s at its input is odd CS 61 C L 25 Representations of Combinational Logic Circuits (11) Garcia, Fall 2011 © UCB

Truth Table Gates (e. g. , majority circ. ) CS 61 C L 25

Truth Table Gates (e. g. , majority circ. ) CS 61 C L 25 Representations of Combinational Logic Circuits (12) Garcia, Fall 2011 © UCB

Truth Table Gates (e. g. , FSM circ. ) PS Input NS Output 00

Truth Table Gates (e. g. , FSM circ. ) PS Input NS Output 00 0 00 1 01 0 00 0 01 1 10 0 00 0 10 1 00 1 CS 61 C L 25 Representations of Combinational Logic Circuits (13) or equivalently… Garcia, Fall 2011 © UCB

Boolean Algebra • George Boole, 19 th Century mathematician • Developed a mathematical system

Boolean Algebra • George Boole, 19 th Century mathematician • Developed a mathematical system (algebra) involving logic • later known as “Boolean Algebra” • Primitive functions: AND, OR and NOT • The power of BA is there’s a one-to-one correspondence between circuits made up of AND, OR and NOT gates and equations in BA + means OR, • means AND, x means NOT CS 61 C L 25 Representations of Combinational Logic Circuits (15) Garcia, Fall 2011 © UCB

Boolean Algebra (e. g. , for majority fun. ) y = a • b

Boolean Algebra (e. g. , for majority fun. ) y = a • b + a • c + b • c y = ab + ac + bc CS 61 C L 25 Representations of Combinational Logic Circuits (16) Garcia, Fall 2011 © UCB

Boolean Algebra (e. g. , for FSM) PS Input NS Output 00 0 00

Boolean Algebra (e. g. , for FSM) PS Input NS Output 00 0 00 1 01 0 00 0 01 1 10 0 00 0 10 1 00 1 or equivalently… y = PS 1 • PS 0 • INPUT CS 61 C L 25 Representations of Combinational Logic Circuits (17) Garcia, Fall 2011 © UCB

BA: Circuit & Algebraic Simplification BA also great for circuit verification Circ X =

BA: Circuit & Algebraic Simplification BA also great for circuit verification Circ X = Circ Y? use BA to prove! CS 61 C L 25 Representations of Combinational Logic Circuits (18) Garcia, Fall 2011 © UCB

Laws of Boolean Algebra CS 61 C L 25 Representations of Combinational Logic Circuits

Laws of Boolean Algebra CS 61 C L 25 Representations of Combinational Logic Circuits (19) Garcia, Fall 2011 © UCB

Boolean Algebraic Simplification Example CS 61 C L 25 Representations of Combinational Logic Circuits

Boolean Algebraic Simplification Example CS 61 C L 25 Representations of Combinational Logic Circuits (20) Garcia, Fall 2011 © UCB

Canonical forms (1/2) Sum-of-products (ORs of ANDs) CS 61 C L 25 Representations of

Canonical forms (1/2) Sum-of-products (ORs of ANDs) CS 61 C L 25 Representations of Combinational Logic Circuits (21) Garcia, Fall 2011 © UCB

Canonical forms (2/2) CS 61 C L 25 Representations of Combinational Logic Circuits (22)

Canonical forms (2/2) CS 61 C L 25 Representations of Combinational Logic Circuits (22) Garcia, Fall 2011 © UCB

Peer Instruction 1) (a+b) • (a+b) = b 123 a: FFF a: FFT 2)

Peer Instruction 1) (a+b) • (a+b) = b 123 a: FFF a: FFT 2) N-input gates can be thought of b: FTF cascaded 2 -input gates. I. e. , b: FTT (a ∆ bc ∆ d ∆ e) = a ∆ (bc ∆ (d ∆ e)) c: TFF where ∆ is one of AND, OR, XOR, NAND d: TFT 3) You can use NOR(s) with clever wiring e: TTF e: TTT to simulate AND, OR, & NOT CS 61 C L 25 Representations of Combinational Logic Circuits (23) Garcia, Fall 2011 © UCB

Peer Instruction Answer 1) (a+b) • (a+b) = aa+ab+ba+bb = 0+b(a+a)+b = b TRUE

Peer Instruction Answer 1) (a+b) • (a+b) = aa+ab+ba+bb = 0+b(a+a)+b = b TRUE 2) (next slide) 3) You can use NOR(s) with clever wiring to simulate AND, OR, & NOT. NOR(a, a)= a+a = a Using this NOT, can we make a NOR an OR? An And? TRUE 123 1) (a+b) • (a+b) = b a: FFF a: FFT 2) N-input gates can be thought of b: FTF cascaded 2 -input gates. I. e. , b: FTT (a ∆ bc ∆ d ∆ e) = a ∆ (bc ∆ (d ∆ e)) c: TFF where ∆ is one of AND, OR, XOR, NAND d: TFT 3) You can use NOR(s) with clever wiring e: TTF e: TTT to simulate AND, OR, & NOT CS 61 C L 25 Representations of Combinational Logic Circuits (24) Garcia, Fall 2011 © UCB

1) Peer Instruction Answer (B) 2) N-input gates can be thought of cascaded 2

1) Peer Instruction Answer (B) 2) N-input gates can be thought of cascaded 2 -input gates. I. e. , (a ∆ bc ∆ d ∆ e) = a ∆ (bc ∆ (d ∆ e)) where ∆ is one of AND, OR, XOR, NAND…FALSE Let’s confirm! CORRECT 3 -input XYZ|AND|OR|XOR|NAND 000| 0 |0 | 1 0 0 0 1 001| 0 |1 | 1 0 1 1 1 010| 0 |1 | 1 0 1 1 1 011| 0 |1 | 0 | 1 0 1 100| 0 |1 | 1 0 101| 0 |1 | 0 | 1 0 0 110| 0 |1 | 0 | 1 0 0 111| 1 |1 | 0 1 1 1 1 CORRECT 2 -input YZ|AND|OR|XOR|NAND 00| 0 |0 | 1 01| 0 |1 | 1 10| 0 |1 | 1 11| 1 |1 | 0 CS 61 C L 25 Representations of Combinational Logic Circuits (25) Garcia, Fall 2011 © UCB

“And In conclusion…” • Pipeline big-delay CL for faster clock • Finite State Machines

“And In conclusion…” • Pipeline big-delay CL for faster clock • Finite State Machines extremely useful • You’ll see them again in 150, 152 & 164 • Use this table and techniques we learned to transform from 1 to another CS 61 C L 25 Representations of Combinational Logic Circuits (26) Garcia, Fall 2011 © UCB