inst eecs berkeley educs 61 c UC Berkeley
inst. eecs. berkeley. edu/~cs 61 c UC Berkeley CS 61 C : Machine Structures Lecture 26 – CPU Design: Designing a Single-cycle CPU, pt 2 2006 -10 -30 Lecturer SOE Dan Garcia www. cs. berkeley. edu/~ddgarcia Halloween plans? Try the Castro, SF! Tomorrow 2005 -10 -31, runs until 11 pm …go at least once… halloweeninthecastro. com Happy Halloween, everyone! CS 61 C L 26 CPU Design : Designing a Single-Cycle CPU II (1) Garcia, Fall 2006 © UCB
How to Design a Processor: step-by-step 1. Analyze instruction set architecture (ISA) => datapath requirements • meaning of each instruction is given by the register transfers • datapath must include storage element for ISA registers • datapath must support each register transfer 2. Select set of datapath components and establish clocking methodology 3. Assemble datapath meeting requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic CS 61 C L 26 CPU Design : Designing a Single-Cycle CPU II (2) Garcia, Fall 2006 © UCB
Step 3: Assemble Data. Path meeting requirements • Register Transfer Requirements Datapath Assembly • Instruction Fetch • Read Operands and Execute Operation CS 61 C L 26 CPU Design : Designing a Single-Cycle CPU II (3) Garcia, Fall 2006 © UCB
3 a: Overview of the Instruction Fetch Unit • Common to all instructions: • Fetch the Instruction: mem[PC] • Update the program counter: § Sequential Code: PC + 4 § Branch and Jump: PC “something else” clk PC Next Address Logic Address Instruction Memory CS 61 C L 26 CPU Design : Designing a Single-Cycle CPU II (4) Instruction Word 32 Garcia, Fall 2006 © UCB
3 b: Add & Subtract • R[rd] R[rs] op R[rt] Ex. : add. U rd, rs, rt • Ra, Rb, and Rw come from instruction’s Rs, Rt, 26 21 16 11 6 and Rd fields 31 op 6 bits rs 5 bits rt 5 bits rd 5 bits shamt 5 bits funct 6 bits 0 • ALUctr and Reg. Wr: control logic after decoding the instruction ALUctr Reg. Wr Rd Rs Rt 5 5 Rw Ra Rb bus. A Reg. File bus. B clk 32 ALU bus. W 5 32 32 Already defined the register file & ALU CS 61 C L 26 CPU Design : Designing a Single-Cycle CPU II (5) Garcia, Fall 2006 © UCB
Clocking Methodology Clk. . . • Storage elements clocked by same edge • Being physical devices, flip-flops (FF) and combinational logic have some delays • Gates: delay from input change to output change • Signals at FF D input must be stable before active clock edge to allow signal to travel within the FF (set-up time), and we have the usual clock-to-Q delay • “Critical path” (longest path through logic) determines length of clock period CS 61 C L 26 CPU Design : Designing a Single-Cycle CPU II (6) Garcia, Fall 2006 © UCB
Register-Register Timing: One complete cycle Clk New Value PC Old Value Instruction Memory Access Time Rs, Rt, Rd, Old Value New Value Op, Func Delay through Control Logic ALUctr Old Value New Value Reg. Wr Old Value bus. A, B Old Value bus. W Old Value New Value Register File Access Time New Value ALU Delay New Value ALUctr Reg. Wr Rd Rs Rt 5 5 Rw Ra Rb bus. A Reg. File bus. B clk CS 61 C L 26 CPU Design : Designing a Single-Cycle CPU II (7) Register Write Occurs Here 32 ALU bus. W 5 32 32 Garcia, Fall 2006 © UCB
3 c: Logical Operations with Immediate • R[rt] = R[rs] op Zero. Ext[imm 16] ] 31 26 op 31 6 bits 21 rs 5 bits 16 rt 5 bits 16 15 5 Rw Ra Rb bus. A Reg. File bus. B clk CS 61 C L 26 CPU Design : Designing a Single-Cycle CPU II (8) 32 ALU bus. W 0 ALUctr Reg. Wr Rd Rs Rt 5 immediate 16 bits 00000000 16 bits 5 0 32 32 Garcia, Fall 2006 © UCB
3 c: Logical Operations with Immediate • R[rt] = R[rs] op Zero. Ext[imm 16] ] 31 26 21 op 31 6 bits Reg. Dst Reg. Wr Rs Rt 5 Rw Ra Rb bus. A Reg. File bus. B 32 16 Zero. Ext clk imm 16 immediate 16 bits 0 immediate 16 bits ALUctr 5 32 ALU 32 0 What about Rt register read? ? 0 5 rt 5 bits 16 15 00000000 16 bits Rd Rt 1 rs 5 bits 16 0 32 1 32 ALUSrc • Already defined 32 -bit MUX; Zero Ext? CS 61 C L 26 CPU Design : Designing a Single-Cycle CPU II (9) Garcia, Fall 2006 © UCB
3 d: Load Operations • R[rt] = Mem[R[rs] + Sign. Ext[imm 16]] Example: lw rt, rs, imm 16 31 26 op 6 bits 21 16 rs 5 bits 0 rt 5 bits immediate 16 bits Reg. Dst Rd Rt 1 Reg. Wr 5 Rs Rt 5 ALUctr 5 Rw Ra Rb bus. A Reg. File bus. B 32 imm 16 16 Zero. Ext clk CS 61 C L 26 CPU Design : Designing a Single-Cycle CPU II (10) 32 0 ALU 32 0 32 1 32 ALUSrc Garcia, Fall 2006 © UCB
3 d: Load Operations • R[rt] = Mem[R[rs] + Sign. Ext[imm 16]] Example: lw rt, rs, imm 16 31 26 21 op 6 bits 16 rs 5 bits 0 rt 5 bits immediate 16 bits ALUctr Reg. Dst Rd Rt 1 Reg. Wr 0 Rs Rt 5 5 5 Rw Ra Rb Reg. File 32 bus. A bus. B 32 imm 16 16 Extender clk 32 0 1 32 Ext. Op CS 61 C L 26 CPU Design : Designing a Single-Cycle CPU II (11) ALU bus. W Memto. Reg Mem. Wr ? 32 Data In ALUSrc clk 32 0 Wr. En Adr Data Memory 1 Garcia, Fall 2006 © UCB
3 e: Store Operations • Mem[ R[rs] + Sign. Ext[imm 16] ] = R[rt] Ex. : sw rt, rs, imm 16 31 26 21 op 6 bits 16 rs 5 bits 0 immediate 16 bits rt 5 bits ALUctr Reg. Dst Rd Rt 1 Reg. Wr 0 Rs Rt 5 5 5 Rw Ra Rb Reg. File 32 bus. A bus. B 32 imm 16 16 Extender clk 32 0 ALU bus. W Memto. Reg Mem. Wr 32 0 32 Wr. En Adr 1 32 Ext. Op CS 61 C L 26 CPU Design : Designing a Single-Cycle CPU II (12) Data In ALUSrc clk Data Memory 1 Garcia, Fall 2006 © UCB
3 e: Store Operations • Mem[ R[rs] + Sign. Ext[imm 16] ] = R[rt] Ex. : sw rt, rs, imm 16 31 26 21 op 6 bits 16 rs 5 bits 0 immediate 16 bits rt 5 bits ALUctr Reg. Dst Rd Rt 1 Reg. Wr 0 Rs Rt 5 5 5 Rw Ra Rb Reg. File 32 bus. A bus. B 32 imm 16 16 Extender clk 32 0 ALU bus. W Memto. Reg Mem. Wr 32 0 32 Wr. En Adr 1 32 Ext. Op CS 61 C L 26 CPU Design : Designing a Single-Cycle CPU II (13) Data In ALUSrc clk Data Memory 1 Garcia, Fall 2006 © UCB
3 f: The Branch Instruction 31 26 op 6 bits 21 rs 5 bits 16 rt 5 bits 0 immediate 16 bits beq rs, rt, imm 16 • mem[PC] Fetch the instruction from memory • Equal = R[rs] == R[rt] Calculate branch condition • if (Equal) Calculate the next instruction’s address § PC = PC + 4 + ( Sign. Ext(imm 16) x 4 ) else § PC = PC + 4 CS 61 C L 26 CPU Design : Designing a Single-Cycle CPU II (14) Garcia, Fall 2006 © UCB
Datapath for Branch Operations • beq rs, rt, imm 16 Datapath generates condition (equal) 31 26 op 6 bits 21 rs 5 bits 16 0 immediate 16 bits rt 5 bits Inst Address Equal n. PC_sel Adder 4 00 clk bus. W 5 ALUctr Rs Rt 5 5 Rw Ra Rb bus. A Reg. File bus. B clk 32 = ALU PC Mux Adder PC Ext imm 16 Reg. Wr 32 32 Already have mux, adder, need special sign extender for PC, need equal compare (sub? ) CS 61 C L 26 CPU Design : Designing a Single-Cycle CPU II (15) Garcia, Fall 2006 © UCB
Putting it All Together: A Single Cycle Datapath Reg. Dst 32 Equal 0 5 5 5 bus. A Rw Ra Rb Reg. File bus. B 32 16 Extender imm 16 Memto. Reg Mem. Wr Rs Rt clk ALUctr 32 = ALU bus. W PC PC Ext Adder Mux 00 Reg. Wr Adder 4 Rt Rd Imm 16 Rd Rt 1 Instruction<31: 0> <0: 15> n. PC_sel Rs <11: 15> Adr <16: 20> <21: 25> Inst Memory 0 32 1 32 Data In clk 32 0 Wr. En Adr Data Memory 1 imm 16 Ext. Op CS 61 C L 26 CPU Design : Designing a Single-Cycle CPU II (16) ALUSrc Garcia, Fall 2006 © UCB
An Abstract View of the Implementation Ideal Instruction Memory PC clk 32 Instruction Rd Rs Rt 5 5 5 Rw Ra Rb Register File clk Control Signals Conditions A 32 ALU Next Address Instruction Address Control B 32 32 Data Addr Ideal Data Memory Data Out Data In clk Datapath CS 61 C L 26 CPU Design : Designing a Single-Cycle CPU II (17) Garcia, Fall 2006 © UCB
Summary: Single cycle datapath ° 5 steps to design a processor • 1. Analyze instruction set => datapath requirements • 2. Select set of datapath components & establish clock methodology • 3. Assemble datapath meeting the requirements • 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. Processor • 5. Assemble the control logic ° Next time! Control Memory Datapath CS 61 C L 26 CPU Design : Designing a Single-Cycle CPU II (19) Input Output Garcia, Fall 2006 © UCB
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