inst eecs berkeley educs 61 c CS 61

inst. eecs. berkeley. edu/~cs 61 c CS 61 C : Machine Structures Lecture 29 – Single Cycle CPU Control II 2004 -11 -05 Andrew Schultz inst. eecs. berkeley. edu/~cs 61 c-tb 13 TB of Memory Soon after delivering a 10, 240 processor supercomputer to NASA, SGI delivers a 2, 048 node system to Japan with the worlds largest memory capacity, 13 TB http: //www. sgi. com/company_info/newsroom/press_releases/2004/november/jaeri. html CS 61 C L 29 Single Cycle CPU Control II (1) Garcia, Fall 2004 © UCB

Review: Single cycle datapath ° 5 steps to design a processor • 1. Analyze instruction set => datapath requirements • 2. Select set of datapath components & establish clock methodology • 3. Assemble datapath meeting the requirements • 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. Processor • 5. Assemble the control logic Input ° Control is the hard part ° MIPS makes that easier Control Memory Datapath • Instructions same size • Source registers always in same place • Immediates same size, location • Operations always on registers/immediates CS 61 C L 29 Single Cycle CPU Control II (2) Output Garcia, Fall 2004 © UCB

Single Cycle Datapath during Or Immediate? 31 26 op 21 rs 16 0 rt immediate • R[rt] = R[rs] OR Zero. Ext[Imm 16] Instruction<31: 0> Zero Mem. Wr = 32 ALUSrc = 0 32 Data In 32 Clk Imm 16 Memto. Reg = Wr. En Adr 32 Mux ALU Extender 16 1 Rs Rd <0: 15> bus. A Rw Ra Rb 32 32 32 -bit Registers bus. B 0 32 imm 16 Rt ALUctr = <11: 15> 5 Rs Rt 5 5 Mux 32 Clk 1 Mux 0 Reg. Wr = bus. W Rt <16: 20> Reg. Dst = Rd Instruction Fetch Unit <21: 25> n. PC_sel = 1 Data Memory Ext. Op = CS 61 C L 29 Single Cycle CPU Control II (3) Garcia, Fall 2004 © UCB

Single Cycle Datapath during Or Immediate? 31 26 op 21 16 rs 0 rt immediate • R[rt] = R[rs] OR Zero. Ext[Imm 16] 1 32 Imm 16 Memto. Reg = 0 Mem. Wr = 0 0 32 Data In 32 ALUSrc = 1 Rs Rd Clk Wr. En Adr 32 Mux ALU Extender 16 Zero <0: 15> bus. A Rw Ra Rb 32 32 32 -bit Registers bus. B 0 32 imm 16 Rt ALUctr = Or <11: 15> Rs Rt 5 5 Mux 32 Clk 1 Mux 0 Reg. Wr = 15 bus. W Rt <16: 20> Reg. Dst = 0 Rd Instruction Fetch Unit <21: 25> n. PC_sel= +4 Instruction<31: 0> 1 Data Memory Ext. Op = 0 CS 61 C L 29 Single Cycle CPU Control II (4) Garcia, Fall 2004 © UCB

The Single Cycle Datapath during Load? 31 26 21 op rs 16 0 rt immediate • R[rt] = Data Memory {R[rs] + Sign. Ext[imm 16]} Instruction<31: 0> 5 bus. A Rw Ra Rb 32 32 32 -bit Registers bus. B 0 32 Rt Zero 32 Imm 16 Memto. Reg = Mem. Wr = 0 32 Data In 32 ALUSrc = Rd Clk Mux ALU 16 Extender imm 16 1 Rs <0: 15> 5 ALUctr = Rt <11: 15> 5 Rs Mux 32 Clk 1 Mux 0 Reg. Wr = bus. W Rt <21: 25> Reg. Dst = Rd Instruction Fetch Unit <16: 20> n. PC_sel= 1 Wr. En Adr Data Memory 32 Ext. Op = CS 61 C L 29 Single Cycle CPU Control II (5) Garcia, Fall 2004 © UCB

The Single Cycle Datapath during Load 31 26 21 op rs 16 0 rt immediate • R[rt] = Data Memory {R[rs] + Sign. Ext[imm 16]} bus. A Rw Ra Rb 32 32 32 -bit Registers bus. B 0 32 Rt Zero 32 Imm 16 Memto. Reg = 1 Mem. Wr = 0 0 32 Data In 32 ALUSrc = 1 Rd Clk Mux ALU 16 Extender imm 16 1 Rs <0: 15> 5 ALUctr = Add Rt <11: 15> 5 Rs Mux 32 Clk 1 Mux 0 Reg. Wr = 1 5 bus. W Rt <16: 20> Reg. Dst = 0 Rd Instruction Fetch Unit <21: 25> n. PC_sel= +4 Instruction<31: 0> 1 Wr. En Adr Data Memory 32 Ext. Op = 1 CS 61 C L 29 Single Cycle CPU Control II (6) Garcia, Fall 2004 © UCB

The Single Cycle Datapath during Store? 31 26 op 21 rs 16 0 rt immediate • Data Memory {R[rs] + Sign. Ext[imm 16]} = R[rt] 1 Mux 0 Reg. Wr = 5 Rs Rt 5 5 Rt ALUctr = bus. A 16 Extender imm 16 1 32 ALUSrc = Clk Memto. Reg = 0 32 Data In 32 Imm 16 Wr. En Adr 32 Mux Rw Ra Rb 32 32 32 -bit Registers bus. B 0 32 Mux 32 Clk Zero Mem. Wr = ALU bus. W Rs Rd <0: 15> Clk <11: 15> Rt <16: 20> Reg. Dst = Rd Instruction Fetch Unit <21: 25> n. PC_sel = Instruction<31: 0> 1 Data Memory Ext. Op = CS 61 C L 29 Single Cycle CPU Control II (7) Garcia, Fall 2004 © UCB

The Single Cycle Datapath during Store 31 26 op 21 rs 16 0 rt immediate • Data Memory {R[rs] + Sign. Ext[imm 16]} = R[rt] 32 0 32 Data In 32 ALUSrc = 1 Rs Rd Clk Wr. En Adr Data Memory 32 Mux 1 <0: 15> 16 Extender imm 16 Imm 16 Memto. Reg = x Zero Mem. Wr = 1 ALU bus. A Rw Ra Rb 32 32 32 -bit Registers bus. B 0 32 Rt <11: 15> ALUctr = Add Rs Rt 5 5 Mux 32 Clk 1 Mux 0 Reg. Wr = 0 5 bus. W Rt <16: 20> Reg. Dst = x Rd Instruction Fetch Unit <21: 25> n. PC_sel= +4 Instruction<31: 0> 1 Ext. Op = 1 CS 61 C L 29 Single Cycle CPU Control II (8) Garcia, Fall 2004 © UCB

The Single Cycle Datapath during Branch? 31 26 op 21 16 rs 0 rt immediate • if (R[rs] - R[rt] == 0) then Zero = 1 ; else Zero = 0 Instruction<31: 0> Data In 32 ALUSrc = 0 32 Clk Wr. En Adr 32 Mux 32 Imm 16 Memto. Reg = Zero Mem. Wr = ALU 16 Extender imm 16 1 Rs Rd <0: 15> bus. A Rw Ra Rb 32 32 32 -bit Registers bus. B 0 32 <11: 15> 5 Rt ALUctr = Rs Rt 5 5 Mux 32 Clk 1 Mux 0 Reg. Wr = bus. W Rt <16: 20> Reg. Dst = Rd Instruction Fetch Unit <21: 25> n. PC_sel= 1 Data Memory Ext. Op = CS 61 C L 29 Single Cycle CPU Control II (9) Garcia, Fall 2004 © UCB

The Single Cycle Datapath during Branch 31 26 op 21 16 rs 0 rt immediate • if (R[rs] - R[rt] == 0) then Zero = 1 ; else Zero = 0 Instruction<31: 0> 32 0 32 Data In 32 ALUSrc = 0 Rs Rd Clk Wr. En Adr 32 Mux 1 <0: 15> 16 Extender imm 16 Imm 16 Memto. Reg = x Zero Mem. Wr = 0 ALU bus. A Rw Ra Rb 32 32 32 -bit Registers bus. B 0 32 <11: 15> 5 Rt ALUctr =Sub Rs Rt 5 5 Mux 32 Clk 1 Mux 0 Reg. Wr = 0 bus. W Rt <16: 20> Reg. Dst = x Rd Instruction Fetch Unit <21: 25> n. PC_sel= “Br” 1 Data Memory Ext. Op = x CS 61 C L 29 Single Cycle CPU Control II (10) Garcia, Fall 2004 © UCB

Instruction Fetch Unit at the End of Branch 31 26 21 op rs 16 rt 0 immediate • if (Zero == 1) then PC = PC + 4 + Sign. Ext[imm 16]*4 ; else PC = PC + 4 Inst Memory n. PC_sel Adr Zero n. PC_MUX_sel Adder 0 PC Mux Adder Extender imm 16 00 4 1 Instruction<31: 0> • What is encoding of n. PC_MUX_sel? • Direct MUX select? • Branch / not branch • Let’s pick 2 nd option Q: What logic gate? Clk CS 61 C L 29 Single Cycle CPU Control II (11) Garcia, Fall 2004 © UCB

Step 4: Given Datapath: RTL -> Control Instruction<31: 0> Rd <0: 15> Rs <11: 15> Rt <16: 20> Op Fun <21: 25> <0: 5> Adr <26: 31> Inst Memory Imm 16 Control n. PC_sel Reg. Wr Reg. Dst Ext. Op ALUSrc ALUctr Mem. Wr Memto. Reg Zero DATA PATH CS 61 C L 29 Single Cycle CPU Control II (12) Garcia, Fall 2004 © UCB

A Summary of the Control Signals (1/2) inst Register Transfer ADD R[rd] <– R[rs] + R[rt]; PC <– PC + 4 ALUsrc = Reg. B, ALUctr = “add”, Reg. Dst = rd, Reg. Wr, n. PC_sel = “+4” SUB R[rd] <– R[rs] – R[rt]; PC <– PC + 4 ALUsrc = Reg. B, ALUctr = “sub”, Reg. Dst = rd, Reg. Wr, n. PC_sel = “+4” ORi R[rt] <– R[rs] + zero_ext(Imm 16); PC <– PC + 4 ALUsrc = Im, Extop = “Z”, ALUctr = “or”, Reg. Dst = rt, Reg. Wr, n. PC_sel =“+4” LOAD R[rt] <– MEM[ R[rs] + sign_ext(Imm 16)]; PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, Memto. Reg, Reg. Dst = rt, Reg. Wr, n. PC_sel = “+4” STORE MEM[ R[rs] + sign_ext(Imm 16)] <– R[rs]; PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, Mem. Wr, n. PC_sel = “+4” BEQ if ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm 16)] || 00 else PC <– PC + 4 n. PC_sel = “Br”, ALUctr = “sub” CS 61 C L 29 Single Cycle CPU Control II (13) Garcia, Fall 2004 © UCB

A Summary of the Control Signals (2/2) See Appendix A func 10 0000 10 0010 We Don’t Care : -) op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 ALUSrc Memto. Reg. Write Mem. Write add 1 0 0 1 0 sub 1 0 0 1 0 ori 0 1 0 lw 0 1 1 1 0 sw x 1 x 0 1 n. PCsel Jump Ext. Op ALUctr<2: 0> 0 0 x Add 0 0 x Subtract 0 0 0 Or 0 0 1 Add Reg. Dst 31 26 21 16 R-type op rs rt I-type op rs rt J-type op CS 61 C L 29 Single Cycle CPU Control II (14) 11 rd jump x x x 0 0 1 0 x 0 1 x xxx Subtract 6 shamt immediate target address beq x 0 0 0 funct add, sub ori, lw, sw, beq jump Garcia, Fall 2004 © UCB

Administrivia • Final exam time/location set Tuesday, December 14 th, 12: 30 – 3: 30 pm At the Hearst Gym (lucky us!) CS 61 C L 29 Single Cycle CPU Control II (15) Garcia, Fall 2004 © UCB

Review: Finite State Machine (FSM) • States represent possible output values. • Transitions represent changes between states based on inputs. • Implement with CL and clocked register feedback. CS 61 C L 29 Single Cycle CPU Control II (16) Garcia, Fall 2004 © UCB

Finite State Machines extremely useful! • They define • How output signals respond to input signals and previous state. • How we change states depending on input signals and previous state • The output signals could be our familiar control signals • Some control signals may only depend on CL, not on state at all… • We could implement very detailed FSMs w/Programmable Logic Arrays CS 61 C L 29 Single Cycle CPU Control II (17) Garcia, Fall 2004 © UCB

Taking advantage of sum-of-products • Since sum-of-products is a convenient notation and way to think about design, offer hardware building blocks that match that notation • One example is Programmable Logic Arrays (PLAs) • Designed so that can select (program) ands, ors, complements after you get the chip • Late in design process, fix errors, figure out what to do later, … CS 61 C L 29 Single Cycle CPU Control II (18) Garcia, Fall 2004 © UCB

Programmable Logic Arrays • Pre-fabricated building block of many AND/OR gates • “Programmed” or “Personalized" by making or breaking connections among gates • Programmable array block diagram for sum of products form Or Programming: • How to combine product terms? • How many outputs? • • • inputs AND array product terms And Programming: • How many inputs? • How to combine inputs? • How many product terms? CS 61 C L 29 Single Cycle CPU Control II (19) OR array outputs • • • Garcia, Fall 2004 © UCB

Enabling Concept • Shared product terms among outputs F 0 F 1 F 2 F 3 example: = = A + A C' + B' C + 1 = uncomplemented in term 0 = complemented in term – = does not participate personality matrix Product term AB B'C AC' B'C' A inputs A B 1 1 – 0 1 – C – 1 0 0 – outputs F 0 F 1 F 2 0 1 1 0 0 1 0 1 1 0 0 CS 61 C L 29 Single Cycle CPU Control II (20) B' C' AB AB A input side: 3 inputs F 3 0 1 0 0 1 output side: 4 outputs 1 = term connected to output 0 = no connection to output reuse of terms; 5 product terms Garcia, Fall 2004 © UCB

Before Programming • All possible connections available before "programming" CS 61 C L 29 Single Cycle CPU Control II (21) Garcia, Fall 2004 © UCB

After Programming • Unwanted connections are "blown" • Fuse (normally connected, break unwanted ones) • Anti-fuse (normally disconnected, make wanted connections) A B C AB B'C AC' B'C' A F 0 CS 61 C L 29 Single Cycle CPU Control II (22) F 1 F 2 F 3 Garcia, Fall 2004 © UCB

Alternate Representation • Short-hand notation--don't have to draw all the wires • X Signifies a connection is present and perpendicular signal is an input to gate notation for implementing F 0 = A B + A' B' F 1 = C D' + C' D A B C D AB A'B' CD' C'D AB+A'B' CD'+C'D CS 61 C L 29 Single Cycle CPU Control II (23) Garcia, Fall 2004 © UCB

Other Programmable Logic Arrays • There are other types of PLAs which can be reprogrammed on the fly • The most common is called a Field Programmable Gate Array (FPGA) • FPGAs are made up of configurable logic blocks (CLBs) and flip-flops which can be programmed by software • Berkeley has on-going research into reconfigurable computing with FPGAs • Check out Brass and BEE 2 projects CS 61 C L 29 Single Cycle CPU Control II (24) Garcia, Fall 2004 © UCB

Peer Instruction<31: 0> Reg. Wr Rs Rt 5 Extender 16 1 32 Clk Imm 16 Mem. Wr Memto. Reg 0 32 Data In 32 ALUSrc Rs Rd Wr. En Adr 32 Mux bus. A Rw Ra Rb 32 32 32 -bit Registers bus. B 0 32 imm 16 Rt Zero ALUctr Mux 32 Clk 5 ALU bus. W 5 <0: 15> Clk 1 Mux 0 <11: 15> Reg. Dst Rt <21: 25> Rd Instruction Fetch Unit <16: 20> n. PC_sel 1 Data Memory 1: Ext. Op 2: A. Mem. To. Reg=‘x’ & ALUctr=‘sub’. SUB or BEQ? 3: 4: B. ALUctr=‘add’. Which 1 signal is different for 5: all 3 of: ADD, LW, & SW? Reg. Dst or Ext. Op? 6: 7: C. “Don’t Care” signals are useful because we can simplify our PLA personality matrix. F / T? 8: CS 61 C L 29 Single Cycle CPU Control II (25) ABC SRF SRT SEF SET BRF BRT BEF BET Garcia, Fall 2004 © UCB

And in Conclusion… Single cycle control ° 5 steps to design a processor • 1. Analyze instruction set => datapath requirements • 2. Select set of datapath components & establish clock methodology • 3. Assemble datapath meeting the requirements • 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. Processor • 5. Assemble the control logic Input ° Control is the hard part ° MIPS makes that easier Control Memory Datapath • Instructions same size • Source registers always in same place • Immediates same size, location • Operations always on registers/immediates CS 61 C L 29 Single Cycle CPU Control II (26) Output Garcia, Fall 2004 © UCB