Improved Random Pattern Delay Fault Coverage Using Inversion

Improved Random Pattern Delay Fault Coverage Using Inversion Test Points Soham Roy, Brandon Stiene, Spencer Millican and Vishwani Agrawal

Pseudo-random Test Ø Practical Built-In-Self-Test scheme • Cheap • Simple • In-field Ø Widely used in previous and current technologies. Ø Quality degraded due to undetected hard-to -detect faults, sometimes called as “Random Pattern Resistant” faults. • Low fault coverage. 2

Random Pattern Resistant Fault Random pattern resistant faults 3

Motivation: To detect random pattern resistant faults ØMethods to improve pseudo-random pattern test: • Deterministic seeding • Pattern weighting • Test-point insertion Ø Test-point: A hardware modification to enhance testability which may change in logic functionality when active. Ø Methods to improve test-point insertion • Location selection algorithms • Enable selection algorithms • Test-point implementation/architecture 4

“Conventional” test-point architecture Control-0 test-point TPE: Test-point enable Control-1 test-point Observe test-point J. Rajski and J. Tyszer, Arithmetic Built-in Self-test for Embedded Systems. Upper Saddle River, NJ, USA: Prentice-Hall, Inc. , 1998. 5

Detriments of “Conventional ”test-point architecture Stuck-at fault model • An active control TP forces a line to a set value, only one stuck-at value can be excited when a control testpoint is active preventing logic on the controlled signal from passing through the test-point. • Control TPs prevent signal transitions and will block all delay faults from passing through the TP. • Control test points prevent delay faults on the output of the TP from being excited. TPE: Test-point enable 6

Detriments of “Conventional ”test-point architecture Transition delay fault model • An active control TP forces a line to a set value, only one stuck-at value can be excited when a control testpoint is active preventing logic on the controlled signal from passing through the test-point. • Control TPs prevent signal transitions and will block all delay faults from passing through the TP. • Control test points prevent delay faults on the output of the TP from being excited. TPE: Test-point enable 7

Inversion-based test-point architecture Stuck-at fault model TPE: Test-point enable Y. Fang and A. Albicki, “Efficient testability enhancement for combinational circuit, ” in Proceedings of International Conference on Computer Design (ICCD), Oct 1995, pp. 168– 172. 8

Inversion-based test-point architecture Transition delay fault model TPE: Test-point enable 9

Detriments of inversion-based test-point architecture Possible detriments of inversionbased test point architecture TPE: Test-point enable 10

Test-point insertion algorithm For every test-point, calculate controllability (CC) and observability (CO) for every line. Generate candidate testpoints Start No End Yes Satisfy target fault coverage or the number of testpoints Fault coverage calculation. Pick best test-point. [Listbased search] Insert test-point into circuit. H. C. Tsai, K. -T. Cheng, C. J. Lin, and S. Bhawmik, “A hybrid algorithm for test point selection for scan-based BIST, ” in Proceedings of the 34 th Design Automation Conference, June 1997, pp. 478– 483. 11

Fault coverage (%) Stuck-at fault coverage for 65, 536 vectors Benchmark circuits ITC’ 99 and ISCAS’ 85 benchmarks 12

Fault coverage (%) Transition delay fault coverage for 65, 536 vectors Benchmark circuits ITC’ 99 and ISCAS’ 85 benchmarks 13

Test-point insertion CPU seconds 400 350 300 Time (s) 250 200 150 100 50 0 CPU: Intel core i 7 -8700 RAM: 8 GB Clock: 3. 2 GHz b 04 b 05 b 07 ITC’ 99 and ISCAS’ 85 benchmarks b 11 b 12 b 13 c 432 c 1355 c 2670 c 3540 Benchmark circuits Conv. Inv. 14

Conclusion Inversion test-points compared to conventional control Conclusions test-points. and Future Directions Ø No negative impact on stuck-at fault coverage. Ø Increase delay fault coverage. 15

Future Directions ØImpact of observe test points on delay fault detection. Conclusions ØImpact of test-points on the detection of redundant and Future faults and producing false failures. Directions 16

Thank You 17